From fbb642d1787032b7bb11c7dd1941179c92b0d6f5 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Fri, 6 Mar 2020 09:11:39 -0800 Subject: [PATCH] drm/i915/tgl: Don't treat unslice registers as masked MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers that we update in a few engine workarounds are not masked registers (i.e., we don't have to write a mask bit in the top 16 bits when updating one of the lower 16 bits). As such, these workarounds should be applied via wa_write_or() rather than wa_masked_en() v2: - Rebase Reported-by: Nick Desaulniers Reported-by: kernelci.org bot References: https://github.com/ClangBuiltLinux/linux/issues/918 Fixes: f85de99d49d2 ("drm/i915/tgl: Move and restrict Wa_1408615072") Fixes: e3747f971acc ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()") Cc: José Roberto de Souza Signed-off-by: Matt Roper Tested-by: Nick Desaulniers Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20200306171139.1414649-1-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 1d42bea21ab08..391f39b1fb266 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1382,8 +1382,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); /* Wa_1408615072:tgl */ - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, - VSUNIT_CLKGATE_DIS_TGL); + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + VSUNIT_CLKGATE_DIS_TGL); } if (IS_TIGERLAKE(i915)) { @@ -1472,12 +1472,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * Wa_1408615072:icl,ehl (vsunit) * Wa_1407596294:icl,ehl (hsunit) */ - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE, - VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); /* Wa_1407352427:icl,ehl */ - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, - PSDUNIT_CLKGATE_DIS); + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + PSDUNIT_CLKGATE_DIS); } if (IS_GEN_RANGE(i915, 9, 12)) { -- 2.39.5