From f8e6a09c64b59eebb1de712ccb7d3203b0184ad6 Mon Sep 17 00:00:00 2001 From: "Abdul Halim, Muhammad Hadi Asyrafi" Date: Thu, 14 May 2020 15:32:43 +0800 Subject: [PATCH] intel: common: Improve mailbox driver readability Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e --- .../soc/common/include/socfpga_mailbox.h | 5 +- plat/intel/soc/common/soc/socfpga_mailbox.c | 59 ++++++++++--------- plat/intel/soc/common/socfpga_sip_svc.c | 18 +++--- 3 files changed, 42 insertions(+), 40 deletions(-) diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index b250b3e90..f44bc0ecc 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -64,6 +64,7 @@ /* Mailbox Definitions */ #define CMD_DIRECT 0 +#define CMD_INDIRECT 1 #define CMD_CASUAL 0 #define CMD_URGENT 1 @@ -123,7 +124,7 @@ #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) -#define MBOX_INDIRECT (1 << 11) +#define MBOX_INDIRECT(val) ((val) << 11) /* RSU Macros */ #define RSU_VERSION_ACMF BIT(8) @@ -140,7 +141,7 @@ void mailbox_set_qspi_direct(void); int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, int len, int urgent, uint32_t *response, int resp_len); int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent); + int len, int urgent, int indirect); int mailbox_read_response(int job_id, uint32_t *response, int resp_len); void mailbox_reset_cold(void); void mailbox_clear_response(void); diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index d066f27b5..cbc6bfba3 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2020, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,7 +32,7 @@ static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); - return 0; + return MBOX_RET_OK; } int mailbox_read_response(int job_id, uint32_t *response, int resp_len) @@ -120,12 +120,12 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, MBOX_STATUS_UA_MASK) ^ (urgent & MBOX_STATUS_UA_MASK)) { mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - return 0; + return MBOX_RET_OK; } mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); INFO("Error: Mailbox did not get UA"); - return -1; + return MBOX_RET_ERROR; } rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); @@ -168,7 +168,7 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response, } int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent) + int len, int urgent, int indirect) { if (urgent) mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); @@ -176,12 +176,12 @@ int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | MBOX_JOB_ID_CMD(job_id) | MBOX_CMD_LEN_CMD(len) | - MBOX_INDIRECT | + MBOX_INDIRECT(indirect) | cmd, args, len); mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - return 0; + return MBOX_RET_OK; } int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, @@ -229,25 +229,21 @@ void mailbox_set_int(int interrupt) void mailbox_set_qspi_open(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, NULL, 0, + CMD_CASUAL, NULL, 0); } void mailbox_set_qspi_direct(void) { - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0, + CMD_CASUAL, NULL, 0); } void mailbox_set_qspi_close(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, NULL, 0); -} - -int mailbox_get_qspi_clock(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, - NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, NULL, 0, + CMD_CASUAL, NULL, 0); } void mailbox_qspi_set_cs(int device_select) @@ -258,19 +254,20 @@ void mailbox_qspi_set_cs(int device_select) cs_setting = (cs_setting << 28); mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, 0, NULL, 0); + 1, CMD_CASUAL, NULL, 0); } void mailbox_reset_cold(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, NULL, 0); + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0, + CMD_CASUAL, NULL, 0); } int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_SUBPARTITION_TABLE, - NULL, 0, 0, (uint32_t *)resp_buf, + NULL, 0, CMD_CASUAL, (uint32_t *)resp_buf, resp_buf_len); } @@ -291,8 +288,9 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) info->retry_counter = ~0; - ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, 0, - (uint32_t *)resp_buf, resp_buf_len); + ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, + CMD_CASUAL, (uint32_t *)resp_buf, + resp_buf_len); if (ret < 0) return ret; @@ -307,13 +305,15 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len) int mailbox_rsu_update(uint32_t *flash_offset) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE, - flash_offset, 2, 0, NULL, 0); + flash_offset, 2, + CMD_CASUAL, NULL, 0); } int mailbox_hps_stage_notify(uint32_t execution_stage) { return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY, - &execution_stage, 1, 0, NULL, 0); + &execution_stage, 1, CMD_CASUAL, + NULL, 0); } int mailbox_init(void) @@ -325,7 +325,8 @@ int mailbox_init(void) mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, NULL, 0); + status = mailbox_send_cmd(0, MBOX_CMD_RESTART, NULL, 0, + CMD_URGENT, NULL, 0); if (status) return status; @@ -333,7 +334,7 @@ int mailbox_init(void) mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE | MBOX_INT_FLAG_UAE); - return 0; + return MBOX_RET_OK; } int intel_mailbox_get_config_status(uint32_t cmd) @@ -341,8 +342,8 @@ int intel_mailbox_get_config_status(uint32_t cmd) int status; uint32_t res, response[6]; - status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response, - sizeof(response) / sizeof(response[0])); + status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0, CMD_CASUAL, response, + ARRAY_SIZE(response)); if (status < 0) return status; @@ -361,7 +362,7 @@ int intel_mailbox_get_config_status(uint32_t cmd) if ((res & SOFTFUNC_STATUS_CONF_DONE) && (res & SOFTFUNC_STATUS_INIT_DONE)) - return 0; + return MBOX_RET_OK; return MBOX_CFGSTAT_STATE_CONFIG; } diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index a20baab4c..b879cfc3b 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,10 +74,9 @@ static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) args[2] = bytes_per_block; buffer->size_written += args[2]; - mailbox_send_cmd_async( - send_id++ % MBOX_MAX_JOB_ID, - MBOX_RECONFIG_DATA, - args, 3, 0); + mailbox_send_cmd_async(send_id++ % MBOX_MAX_JOB_ID, + MBOX_RECONFIG_DATA, args, 3, + CMD_CASUAL, CMD_INDIRECT); buffer->subblocks_sent++; max_blocks--; @@ -154,7 +153,7 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr, while (*count < 3) { resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, - resp, sizeof(resp) / sizeof(resp[0])); + resp, ARRAY_SIZE(resp)); if (resp_len < 0) break; @@ -208,10 +207,10 @@ static int intel_fpga_config_start(uint32_t config_type) mailbox_clear_response(); - mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); + mailbox_send_cmd(1, MBOX_CMD_CANCEL, NULL, 0, CMD_CASUAL, NULL, 0); - status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, - response, sizeof(response) / sizeof(response[0])); + status = mailbox_send_cmd(1, MBOX_RECONFIG, NULL, 0, CMD_CASUAL, + response, ARRAY_SIZE(response)); if (status < 0) return status; @@ -449,6 +448,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, u_register_t x5, x6; int mbox_status, len_in_resp; + switch (smc_fid) { case SIP_SVC_UID: /* Return UID to the caller */ -- 2.39.5