From e8166d3e5937b8db43921b5049672b16af7f58e0 Mon Sep 17 00:00:00 2001 From: Madhukar Pappireddy Date: Wed, 22 Mar 2023 15:27:22 -0500 Subject: [PATCH] feat(sbsa): helper api for refreshing watchdog timer This patch adds a helper API to explicitly refresh SBSA secure watchdog timer. Please refer section A.3 of the following spec: https://developer.arm.com/documentation/den0029/latest/ Change-Id: I2d0943792aea0092bee1e51d74b908348587e66b Signed-off-by: Madhukar Pappireddy --- changelog.yaml | 3 +++ drivers/arm/sbsa/sbsa.c | 8 +++++++- include/drivers/arm/sbsa.h | 10 ++++++++-- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/changelog.yaml b/changelog.yaml index 6dbb9b20d..c969b2c56 100644 --- a/changelog.yaml +++ b/changelog.yaml @@ -877,6 +877,9 @@ subsections: deprecated: - drivers/tzc380 + - title: SBSA + scope: sbsa + - title: Marvell scope: marvell-drivers diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c index 79c6f2620..a88e20c04 100644 --- a/drivers/arm/sbsa/sbsa.c +++ b/drivers/arm/sbsa/sbsa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,3 +40,9 @@ void sbsa_wdog_stop(uintptr_t base) { mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); } + +/* Refresh the secure watchdog timer explicitly */ +void sbsa_wdog_refresh(uintptr_t refresh_base) +{ + mmio_write_32(refresh_base + SBSA_WDOG_WRR_OFFSET, SBSA_WDOG_WRR_REFRESH); +} diff --git a/include/drivers/arm/sbsa.h b/include/drivers/arm/sbsa.h index 9403634f7..4ca71942e 100644 --- a/include/drivers/arm/sbsa.h +++ b/include/drivers/arm/sbsa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,12 @@ #include -/* Register Offsets */ +/* SBSA Secure Watchdog Register Offsets */ +/* Refresh frame */ +#define SBSA_WDOG_WRR_OFFSET UL(0x000) +#define SBSA_WDOG_WRR_REFRESH UL(0x1) + +/* Control and status frame */ #define SBSA_WDOG_WCS_OFFSET UL(0x000) #define SBSA_WDOG_WOR_LOW_OFFSET UL(0x008) #define SBSA_WDOG_WOR_HIGH_OFFSET UL(0x00C) @@ -20,5 +25,6 @@ void sbsa_wdog_start(uintptr_t base, uint64_t ms); void sbsa_wdog_stop(uintptr_t base); +void sbsa_wdog_refresh(uintptr_t refresh_base); #endif /* SBSA_H */ -- 2.39.5