From dbd0a6606e52f095f6b96dd38103123de567a1e1 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Thu, 24 Oct 2019 11:56:07 +0800 Subject: [PATCH] drm/amdgpu: update the method to set kcq queue mask Use a common method to set queue mask before set kiq resource. The value of queue mask must suitablt for the designated form. Signed-off-by: Likun Gao Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 0103acc574742..ed212c070e8ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -485,6 +485,19 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) return amdgpu_ring_test_helper(kiq_ring); } +int amdgpu_gfx_kcq_queue_mask_transform(struct amdgpu_device *adev, + int queue_bit) +{ + int mec, pipe, queue; + int queue_kcq_bit = 0; + + amdgpu_gfx_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); + + queue_kcq_bit = mec * 4 * 8 + pipe * 8 + queue; + + return queue_kcq_bit; +} + int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) { struct amdgpu_kiq *kiq = &adev->gfx.kiq; @@ -507,7 +520,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) break; } - queue_mask |= (1ull << i); + queue_mask |= (1ull << amdgpu_gfx_kcq_queue_mask_transform(adev, i)); } DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, -- 2.39.5