From d9e4c3781cae0d746a2f99486ff1c93da6e510ed Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Fri, 27 Aug 2021 14:14:43 +0200 Subject: [PATCH] arm: a37xx: pci: Disable returning CRS response MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit There was mistake in commit a38d8e93a813 ("arm: a37xx: pci: Fix handling PIO config error responses"). U-Boot does not support handling of CRS return value for PCI_VENDOR_ID config read request and also does not set CRSSVE bit. Therefore disable returning CRS response for now. Signed-off-by: Pali Rohár Fixes: a38d8e93a813 ("arm: a37xx: pci: Fix handling PIO config error responses") Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 815b26162f..d3ef8f203d 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -358,7 +358,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - allow_crs = (offset == PCI_VENDOR_ID) && (size == 4); + /* + * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to + * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and + * only when CRSSVE bit in Root Port PCIe device is enabled. In all + * other error PCIe Root Complex must return all-ones. + * Aardvark HW does not have Root Port PCIe device and U-Boot does not + * implement emulation of this device. + * U-Boot currently does not support handling of CRS return value for + * PCI_VENDOR_ID config read request and also does not set CRSSVE bit. + * Therefore disable returning CRS response for now. + */ + allow_crs = false; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, -- 2.39.5