From d1a8b8d0c8b3a6bf81d36a4ee6334da5a2408979 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 11 Jun 2020 08:52:38 -0600 Subject: [PATCH] dt-bindings: phy: qcom: Fix missing 'ranges' and example addresses The QCom QMP PHY bindings have child nodes with translatable (MMIO) addresses, so a 'ranges' property is required in the parent node. Additionally, the examples default to 1 address and size cell, so let's fix that, too. Fixes: 555ded919abb ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Manu Gautam Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 20 ++++++---- .../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 38 ++++++++++--------- 2 files changed, 33 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 973b2d196f466..f80f8896d5276 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -44,6 +44,8 @@ properties: "#size-cells": enum: [ 1, 2 ] + ranges: true + clocks: minItems: 1 maxItems: 4 @@ -87,6 +89,7 @@ required: - "#clock-cells" - "#address-cells" - "#size-cells" + - ranges - clocks - clock-names - resets @@ -281,10 +284,11 @@ examples: #include usb_2_qmpphy: phy-wrapper@88eb000 { compatible = "qcom,sdm845-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x18c>; + reg = <0x088eb000 0x18c>; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x088eb000 0x2000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, @@ -299,11 +303,11 @@ examples: vdda-phy-supply = <&vdda_usb2_ss_1p2>; vdda-pll-supply = <&vdda_usb2_ss_core>; - usb_2_ssphy: phy@88eb200 { - reg = <0 0x088eb200 0 0x128>, - <0 0x088eb400 0 0x1fc>, - <0 0x088eb800 0 0x218>, - <0 0x088eb600 0 0x70>; + usb_2_ssphy: phy@200 { + reg = <0x200 0x128>, + <0x400 0x1fc>, + <0x800 0x218>, + <0x600 0x70>; #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml index b770e637df1d9..6e2487501457a 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml @@ -34,6 +34,8 @@ properties: "#size-cells": enum: [ 1, 2 ] + ranges: true + clocks: items: - description: Phy aux clock. @@ -86,6 +88,7 @@ required: - "#clock-cells" - "#address-cells" - "#size-cells" + - ranges - clocks - clock-names - resets @@ -100,12 +103,13 @@ examples: #include usb_1_qmpphy: phy-wrapper@88e9000 { compatible = "qcom,sdm845-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; + reg = <0x088e9000 0x18c>, + <0x088e8000 0x10>; reg-names = "reg-base", "dp_com"; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x088e9000 0x1000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, @@ -120,17 +124,17 @@ examples: vdda-phy-supply = <&vdda_usb2_ss_1p2>; vdda-pll-supply = <&vdda_usb2_ss_core>; - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x128>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x128>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + phy@200 { + reg = <0x200 0x128>, + <0x400 0x200>, + <0xc00 0x218>, + <0x600 0x128>, + <0x800 0x200>, + <0xa00 0x100>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; }; + }; -- 2.39.5