From cc76e7b6750ae637254812a0c82be2f059117ea6 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Fri, 18 Aug 2017 10:23:42 -0700 Subject: [PATCH] drm/i915: Re-enable per-engine reset for Broxton The corruption in CSB mmio reads we were seeing has been tracked down to incorrectly touching forcewake of all domains, following an engine reset. It is still a mistery why we only catched this in Broxton, since it could happen in any platform. With that fix already merged, commit 37c34927e792 ("drm/i915: Stop touching forcewake following a gen6+ engine reset"), lets try to enable per-engine resets in Broxton one more time. This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for Broxton"). Cc: Chris Wilson Signed-off-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170818172342.7282-1-michel.thierry@intel.com Tested-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_pci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 09d97e0990b78..a1e6b696bcfa0 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -398,7 +398,6 @@ static const struct intel_device_info intel_broxton_info = { GEN9_LP_FEATURES, .platform = INTEL_BROXTON, .ddb_size = 512, - .has_reset_engine = false, }; static const struct intel_device_info intel_geminilake_info = { -- 2.39.5