From ad6eb1951b986f30635025bbdf29e257b6b1e362 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 26 Oct 2022 16:38:53 +0800 Subject: [PATCH] fix(imx8m): update poweroff related SNVS_LPCR bits only Function imx_system_off() writes SNVS_LPCR register to power off the SoC without bit masking. This clears other bits like LPWUI_EN and breaks the function of SoC wake-up using RTC alarm. Fix it by updating poweroff related bits only. Signed-off-by: Shawn Guo Change-Id: If641af4dc1103c67e1a645c03bb36a5f56665aef --- plat/imx/imx8m/imx8m_psci_common.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c index 4df4f8edc..d396902cd 100644 --- a/plat/imx/imx8m/imx8m_psci_common.c +++ b/plat/imx/imx8m/imx8m_psci_common.c @@ -229,8 +229,11 @@ int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie) void __dead2 imx_system_off(void) { - mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV | - SNVS_LPCR_DP_EN | SNVS_LPCR_TOP); + uint32_t val; + + val = mmio_read_32(IMX_SNVS_BASE + SNVS_LPCR); + val |= SNVS_LPCR_SRTC_ENV | SNVS_LPCR_DP_EN | SNVS_LPCR_TOP; + mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, val); while (1) ; -- 2.39.5