From ab49840272cfa595327fa1212a5a44287b9ac986 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Thu, 29 Jul 2021 10:00:01 -0700 Subject: [PATCH] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit DG2 supports compute DSS and has the same maximum number of DSS and EU as XeHP SDV. Signed-off-by: Matt Roper Reviewed-by: Caz Yokoyama Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-12-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 3a2ff0e00b657..a648818eafa52 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -145,7 +145,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt) * across the entire device. Then calculate out the DSS for each * workload type within that software slice. */ - if (IS_XEHPSDV(gt->i915)) + if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915)) intel_sseu_set_info(sseu, 1, 32, 16); else intel_sseu_set_info(sseu, 1, 6, 16); -- 2.39.5