From ab062f0510d42b2019667e3f4df82a1f57121412 Mon Sep 17 00:00:00 2001 From: Sona Mathew Date: Tue, 14 Mar 2023 16:50:36 -0500 Subject: [PATCH] fix(cpus): workaround platforms non-arm interconnect The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 EL3 provides an appropriate return value via errata ABI when the kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the appropriate erratum ID. Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850 Signed-off-by: Sona Mathew --- docs/design/cpu-specific-build-macros.rst | 49 +++++++++++++ lib/cpus/cpu-ops.mk | 43 ++++++++++++ services/std_svc/errata_abi/cpu_errata_info.h | 6 +- services/std_svc/errata_abi/errata_abi_main.c | 68 ++++++++++++++----- 4 files changed, 147 insertions(+), 19 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 0f1f92aea..758d62be9 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -317,6 +317,11 @@ For Cortex-A78, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and it is still open. +- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 + CPU, this erratum affects system configurations that do not use an ARM + interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 + and r1p2 and it is still open. + - ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and it is still open. @@ -347,6 +352,11 @@ For Cortex-A78 AE, the following errata build flags are defined : Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. +- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to + Cortex-A78 AE CPU. This erratum affects system configurations that do not use + an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and + r0p2. This erratum is still open. + For Cortex-A78C, the following errata build flags are defined : - ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to @@ -373,6 +383,11 @@ For Cortex-A78C, the following errata build flags are defined : Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This erratum is still open. +- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to + Cortex-A78C CPU, this erratum affects system configurations that do not use + an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 + and is still open. + - ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. This erratum is still open. @@ -488,6 +503,11 @@ For Neoverse V1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. It is still open. +- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 + CPU, this erratum affects system configurations that do not use an ARM + interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. + It has been fixed in r1p2. + - ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the CPU. It is still open. @@ -500,6 +520,13 @@ For Neoverse V1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the CPU. It is still open. +For Neoverse V2, the following errata build flags are defined : + +- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 + CPU, this affects system configurations that do not use and ARM interconnect + IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed + in r0p2. + For Cortex-A710, the following errata build flags are defined : - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to @@ -558,6 +585,11 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 + CPU, and applies to system configurations that do not use and ARM + interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and + is still open. + - ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. @@ -610,6 +642,11 @@ For Neoverse N2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed in r0p3. +- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 + CPU, this erratum affects system configurations that do not use and ARM + interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. + It is fixed in r0p3. + For Cortex-X2, the following errata build flags are defined : - ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 @@ -647,6 +684,11 @@ For Cortex-X2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 + CPU and affects system configurations that do not use an ARM interconnect IP. + This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is + still open. + - ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. @@ -709,6 +751,13 @@ For Cortex-A510, the following errata build flags are defined : Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. +For Cortex-A715, the following errata build flags are defined : + +- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715 + CPU and affects system configurations that do not use an ARM interconnect + IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed + in r1p2. + DSU Errata Workarounds ---------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 82a4890cf..e16c8e495 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -324,6 +324,11 @@ CPU_FLAG_LIST += ERRATA_A78_2376745 # to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78_2395406 +# Flag to apply erratum 2712571 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. +# It is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_A78_2712571 + # Flag to apply erratum 2742426 workaround during reset. This erratum # applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still # open. @@ -362,6 +367,11 @@ CPU_FLAG_LIST += ERRATA_A78C_1827430 # to revision r0p0 of the A78C cpu. It is fixed in r0p1. CPU_FLAG_LIST += ERRATA_A78C_1827440 +# Flag to apply erratum 2712574 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, r0p1 and r0p2 of the A78 AE cpu. +# It is still open. +CPU_FLAG_LIST += ERRATA_A78_AE_2712574 + # Flag to apply erratum 2132064 workaround during reset. This erratum applies # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2132064 @@ -378,6 +388,11 @@ CPU_FLAG_LIST += ERRATA_A78C_2376749 # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2395411 +# Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p1 and r0p2 of the A78C cpu. +# It is still open. +CPU_FLAG_LIST += ERRATA_A78C_2712575 + # Flag to apply erratum 2772121 workaround during powerdown. This erratum # applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2772121 @@ -509,6 +524,11 @@ CPU_FLAG_LIST += ERRATA_V1_2294912 # to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is still open. CPU_FLAG_LIST += ERRATA_V1_2372203 +# Flag to apply erratum 2701953 workaround to non-arm interconnect ip. This +# erratum applies to revisions r0p0, r1p0, r1p1 of the Neoverse V1 cpu, +# it is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_V1_2701953 + # Flag to apply erratum 2743093 workaround during powerdown. This erratum # applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is # still open. @@ -581,6 +601,11 @@ CPU_FLAG_LIST += ERRATA_A710_2008768 # to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. CPU_FLAG_LIST += ERRATA_A710_2371105 +# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This +# erratum applies to revision r0p0, r1p0, r2p0, r2p1 of the Cortex-A710 cpu +# and is still open. +CPU_FLAG_LIST += ERRATA_A710_2701952 + # Flag to apply erratum 2768515 workaround during power down. This erratum # applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is # still open. @@ -638,6 +663,11 @@ CPU_FLAG_LIST += ERRATA_N2_2376738 # to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2388450 +# Flag to apply erratum 2728475 workaround for non-arm interconnect ip. This +# erratum applies to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in +# r0p3. +CPU_FLAG_LIST += ERRATA_N2_2728475 + # Flag to apply erratum 2743089 workaround during during powerdown. This erratum # applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3. CPU_FLAG_LIST += ERRATA_N2_2743089 @@ -682,6 +712,11 @@ CPU_FLAG_LIST += ERRATA_X2_2282622 # to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1. CPU_FLAG_LIST += ERRATA_X2_2371105 +# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, r1p0, r2p0, r2p1 of the Cortex-x2 cpu +# and is still open. +CPU_FLAG_LIST += ERRATA_X2_2701952 + # Flag to apply erratum 2768515 workaround during power down. This erratum # applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is # still open. @@ -743,6 +778,14 @@ CPU_FLAG_LIST += ERRATA_A510_2666669 # Cortex-A510 cpu and is fixed in r1p3. CPU_FLAG_LIST += ERRATA_A510_2684597 +# Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, rop1. Fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2719103 + +# Flag to apply erratum 2701951 workaround for non-arm interconnect ip. +# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_A715_2701951 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_798953 diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h index ad05724f8..671a6949d 100644 --- a/services/std_svc/errata_abi/cpu_errata_info.h +++ b/services/std_svc/errata_abi/cpu_errata_info.h @@ -39,11 +39,12 @@ #include #endif -#define MAX_ERRATA_ENTRIES 15 +#define MAX_ERRATA_ENTRIES 16 #define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1) -#define UNDEF_ERRATA {UINT_MAX, UCHAR_MAX, UCHAR_MAX, false} +/* Default values for unused memory in the array */ +#define UNDEF_ERRATA {UINT_MAX, UCHAR_MAX, UCHAR_MAX, false, false} #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) @@ -52,7 +53,6 @@ /* * CPU specific values for errata handling */ - struct em_cpu{ unsigned int em_errata_id; unsigned char em_rxpx_lo; /* lowest revision of errata applicable for the cpu */ diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c index d473df6e2..bf9409d06 100644 --- a/services/std_svc/errata_abi/errata_abi_main.c +++ b/services/std_svc/errata_abi/errata_abi_main.c @@ -200,10 +200,12 @@ struct em_cpu_list cpu_list[] = { [6] = {2242635, 0x10, 0x12, ERRATA_A78_2242635}, [7] = {2376745, 0x00, 0x12, ERRATA_A78_2376745}, [8] = {2395406, 0x00, 0x12, ERRATA_A78_2395406}, - [9] = {2742426, 0x00, 0x12, ERRATA_A78_2742426}, - [10] = {2772019, 0x00, 0x12, ERRATA_A78_2772019}, - [11] = {2779479, 0x00, 0x12, ERRATA_A78_2779479}, - [12 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [9] = {2712571, 0x00, 0x12, ERRATA_A78_2712571, \ + ERRATA_NON_ARM_INTERCONNECT}, + [10] = {2742426, 0x00, 0x12, ERRATA_A78_2742426}, + [11] = {2772019, 0x00, 0x12, ERRATA_A78_2772019}, + [12] = {2779479, 0x00, 0x12, ERRATA_A78_2779479}, + [13 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_A78_H_INC */ @@ -216,7 +218,9 @@ struct em_cpu_list cpu_list[] = { [1] = {1951502, 0x00, 0x01, ERRATA_A78_AE_1951502}, [2] = {2376748, 0x00, 0x01, ERRATA_A78_AE_2376748}, [3] = {2395408, 0x00, 0x01, ERRATA_A78_AE_2395408}, - [4 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [4] = {2712574, 0x00, 0x02, ERRATA_A78_AE_2712574, \ + ERRATA_NON_ARM_INTERCONNECT}, + [5 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_A78_AE_H_INC */ @@ -229,9 +233,11 @@ struct em_cpu_list cpu_list[] = { [1] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638}, [2] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749}, [3] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411}, - [4] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121}, - [5] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484}, - [6 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [4] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \ + ERRATA_NON_ARM_INTERCONNECT}, + [5] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121}, + [6] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484}, + [7 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_A78C_H_INC */ @@ -287,9 +293,11 @@ struct em_cpu_list cpu_list[] = { [9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392}, [10] = {2294912, 0x00, 0x11, ERRATA_V1_2294912}, [11] = {2372203, 0x00, 0x11, ERRATA_V1_2372203}, - [12] = {2743093, 0x00, 0x12, ERRATA_V1_2743093}, - [13] = {2779461, 0x00, 0x12, ERRATA_V1_2779461}, - [14 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [12] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \ + ERRATA_NON_ARM_INTERCONNECT}, + [13] = {2743093, 0x00, 0x12, ERRATA_V1_2743093}, + [14] = {2779461, 0x00, 0x12, ERRATA_V1_2779461}, + [15 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* NEOVERSE_V1_H_INC */ @@ -312,7 +320,9 @@ struct em_cpu_list cpu_list[] = { [11] = {2282622, 0x00, 0x21, ERRATA_A710_2282622}, [12] = {2291219, 0x00, 0x20, ERRATA_A710_2291219}, [13] = {2371105, 0x00, 0x20, ERRATA_A710_2371105}, - [14] = {2768515, 0x00, 0x21, ERRATA_A710_2768515} + [14] = {2701952, 0x00, 0x21, ERRATA_A710_2701952, \ + ERRATA_NON_ARM_INTERCONNECT}, + [15] = {2768515, 0x00, 0x21, ERRATA_A710_2768515} } }, #endif /* CORTEX_A710_H_INC */ @@ -334,8 +344,10 @@ struct em_cpu_list cpu_list[] = { [10] = {2326639, 0x00, 0x00, ERRATA_N2_2326639}, [11] = {2376738, 0x00, 0x00, ERRATA_N2_2376738}, [12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450}, - [13] = {2743089, 0x00, 0x02, ERRATA_N2_2743089}, - [14 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \ + ERRATA_NON_ARM_INTERCONNECT}, + [14] = {2743089, 0x00, 0x02, ERRATA_N2_2743089}, + [15 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* NEOVERSE_N2_H_INC */ @@ -353,8 +365,10 @@ struct em_cpu_list cpu_list[] = { [6] = {2216384, 0x00, 0x20, ERRATA_X2_2216384}, [7] = {2282622, 0x00, 0x21, ERRATA_X2_2282622}, [8] = {2371105, 0x00, 0x21, ERRATA_X2_2371105}, - [9] = {2768515, 0x00, 0x21, ERRATA_X2_2768515}, - [10 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [9] = {2701952, 0x00, 0x21, ERRATA_X2_2701952, \ + ERRATA_NON_ARM_INTERCONNECT}, + [10] = {2768515, 0x00, 0x21, ERRATA_X2_2768515}, + [11 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_X2_H_INC */ @@ -378,6 +392,28 @@ struct em_cpu_list cpu_list[] = { } }, #endif /* CORTEX_A510_H_INC */ + +#if NEOVERSE_V2_H_INC +{ + .cpu_partnumber = NEOVERSE_V2_MIDR, + .cpu_errata_list = { + [0] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \ + ERRATA_NON_ARM_INTERCONNECT}, + [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* NEOVERSE_V2_H_INC */ + +#if CORTEX_A715_H_INC +{ + .cpu_partnumber = CORTEX_MAKALU_MIDR, + .cpu_errata_list = { + [0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \ + ERRATA_NON_ARM_INTERCONNECT}, + [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A715_H_INC */ }; /* -- 2.39.5