From a1cd6c8b8f03930faf110234fa8366c4ff25085d Mon Sep 17 00:00:00 2001 From: Linus Walleij <linus.walleij@linaro.org> Date: Tue, 9 Jul 2019 13:41:53 +0200 Subject: [PATCH] pinctrl: aspeed: Fix missed include Some SPDX churn made my fixes drop an important include from the Aspeed pinctrl header. Fix it up. Cc: Andrew Jeffery <andrew@aj.id.au> Reported-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 9b20b1c03802e..b7790395aeade 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -16,6 +16,8 @@ #include <linux/pinctrl/pinconf-generic.h> #include <linux/regmap.h> +#include "pinmux-aspeed.h" + /* * The ASPEED SoCs provide typically more than 200 pins for GPIO and other * functions. The SoC function enabled on a pin is determined on a priority -- 2.39.5