From 9965efe0e1314412cc1badf60079a55b6e2a8fa7 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 13 May 2012 09:54:09 +0100 Subject: [PATCH] drm/i915: Enable the PCH PLL for all generations after link training Hidden away within one chipset specific path was the necessary logic to turn on the PLL. This needs to be done everywhere in order for us to drive any display! As such as soon as we tested on a non-CougarPoint chipset, we failed to bring up any DisplayPorts and generated a nice set of assertion failures in the process. At least one part of our logic is working, the part that assumes that we have no idea what we are doing. Reported-by: guang.a.yang@intel.com References: https://bugs.freedesktop.org/show_bug.cgi?id=49712 Signed-off-by: Chris Wilson Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9dc42bf557bed..f3d39f4f6909d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2796,14 +2796,14 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc); + intel_enable_pch_pll(intel_crtc); + if (HAS_PCH_LPT(dev)) { DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); lpt_program_iclkip(crtc); } else if (HAS_PCH_CPT(dev)) { u32 sel; - intel_enable_pch_pll(intel_crtc); - temp = I915_READ(PCH_DPLL_SEL); switch (pipe) { default: -- 2.39.5