From 8e9c2f621893ae2cc57c34fa96ece011eebd94b7 Mon Sep 17 00:00:00 2001 From: "Robert M. Fosha" Date: Tue, 25 Jun 2019 09:41:07 -0700 Subject: [PATCH] drm/i915/guc: Add debug capture of GuC exception Detect GuC firmware load failure due to an exception during execution in GuC firmware. Output the GuC EIP where exception occurred to dmesg for GuC debug information. v2: correct typos, change debug message and error code returned for GuC exception (Michal) Signed-off-by: Robert M. Fosha Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190625164107.21512-1-robert.m.fosha@intel.com --- drivers/gpu/drm/i915/intel_guc_fw.c | 7 +++++++ drivers/gpu/drm/i915/intel_guc_reg.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index 72cdafd9636ad..970f39ef248bb 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -197,6 +197,7 @@ static inline bool guc_ready(struct intel_guc *guc, u32 *status) static int guc_wait_ucode(struct intel_guc *guc) { + struct drm_i915_private *i915 = guc_to_i915(guc); u32 status; int ret; @@ -216,6 +217,12 @@ static int guc_wait_ucode(struct intel_guc *guc) ret = -ENOEXEC; } + if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) { + DRM_ERROR("GuC firmware exception. EIP: %#x\n", + intel_uncore_read(&i915->uncore, SOFT_SCRATCH(13))); + ret = -ENXIO; + } + if (ret == 0 && !guc_xfer_completed(guc, &status)) { DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n", status); diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index a214f8b71929b..d90b88fadb5e5 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -37,6 +37,7 @@ #define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT) #define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT) #define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT) +#define GS_UKERNEL_EXCEPTION (0x70 << GS_UKERNEL_SHIFT) #define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT) #define GS_MIA_SHIFT 16 #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT) -- 2.39.5