From 6e3c7d017c730bd0ea12e935cc3172b36680c443 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 15 Jul 2015 16:17:45 +0100 Subject: [PATCH] MIPS: dump_tlb: Only dump PageGrain if interesting The PageGrain register may not exist if certain architectural features aren't present, therefore only print out its value when dumping the TLB registers if it is expected to contain fields relevant to the TLB. Fixes: 35df0fbdfbda ("MIPS: Add SysRq operation to dump TLBs on all CPUs") Reported-by: Joshua Kinard Reported-by: Maciej W. Rozycki Signed-off-by: James Hogan Cc: Joshua Kinard Cc: Maciej W. Rozycki Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10723/ Signed-off-by: Ralf Baechle --- arch/mips/lib/dump_tlb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 519ededbf9a4c..2ab83be14ffaa 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -23,7 +23,8 @@ void dump_tlb_regs(void) pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0()); pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1()); pr_info("Wired : %0x\n", read_c0_wired()); - pr_info("PageGrain: %0x\n", read_c0_pagegrain()); + if (cpu_has_small_pages || cpu_has_rixi || cpu_has_xpa) + pr_info("PageGrain: %0x\n", read_c0_pagegrain()); if (cpu_has_htw) { pr_info("PWField : %0*lx\n", field, read_c0_pwfield()); pr_info("PWSize : %0*lx\n", field, read_c0_pwsize()); -- 2.39.5