From 6c14ebb7245b174eb91d9b01f91c18dc4c7910c6 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 18 Sep 2012 23:10:24 +0000 Subject: [PATCH] mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQ Upon completion of a MMC_WRITE_MULTIPLE_BLOCK command MMCIF issues an IRQ with the DTRANE bit set and often with one or several of CMD12 bits set. If those interrupts are not acknowledged, an additional interrupt can be produced and will be delivered later, possibly, when the transaction has already been completed. To prevent this from happening, CMD12 completion interrupt sources have to be cleared too upon reception of an DTRANE IRQ. Signed-off-by: Guennadi Liakhovetski Tested-by: Tetsuyuki Kobayashi Signed-off-by: Chris Ball --- drivers/mmc/host/sh_mmcif.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 5d8142773fac0..6df3dc3164f73 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -1213,7 +1213,9 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); } else if (state & INT_DTRANE) { - sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); + sh_mmcif_writel(host->addr, MMCIF_CE_INT, + ~(INT_CMD12DRE | INT_CMD12RBE | + INT_CMD12CRE | INT_DTRANE)); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); } else if (state & INT_CMD12RBE) { sh_mmcif_writel(host->addr, MMCIF_CE_INT, -- 2.39.5