From 632ab6cb84ebe05e1bf2ac224cb5f7a14f83d44d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 13 Dec 2022 05:46:06 +0100 Subject: [PATCH] ARM: imx: bootaux: Fix macro misuse There are no CONFIG_{TOOLS_,SPL_,TPL_,}IMX8M macros, nor is there one for ARM64. Use plain IS_ENABLED(CONFIG_IMX8M) and IS_ENABLED(CONFIG_ARM64) to avoid expanding the {TOOLS_,SPL_,TPL_,} part. Fixes: 9d22a64ea09d ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx_bootaux.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 8115bf40f1..433c1f80ce 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -15,7 +15,7 @@ #include /* Just to avoid build error */ -#if CONFIG_IS_ENABLED(IMX8M) +#if IS_ENABLED(CONFIG_IMX8M) #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) #define SRC_M4_ENABLE_MASK BIT(0) #define SRC_M4_REG_OFFSET 0 @@ -106,7 +106,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) if (!pc) return CMD_RET_FAILURE; - if (!CONFIG_IS_ENABLED(ARM64)) + if (!IS_ENABLED(CONFIG_ARM64)) stack = 0x0; } else { /* @@ -128,7 +128,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) flush_dcache_all(); /* Enable M4 */ - if (CONFIG_IS_ENABLED(IMX8M)) { + if (IS_ENABLED(CONFIG_IMX8M)) { arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL); } else { clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, @@ -143,7 +143,7 @@ int arch_auxiliary_core_check_up(u32 core_id) struct arm_smccc_res res; unsigned int val; - if (CONFIG_IS_ENABLED(IMX8M)) { + if (IS_ENABLED(CONFIG_IMX8M)) { arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res); return res.a0; } -- 2.39.5