From 61b618c3ebd5b4a4d47e1f926c8d8af57e1b259e Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 20 Apr 2022 09:57:45 +0100 Subject: [PATCH] ARM: 9199/1: spectre-bhb: use local DSB and elide ISB in loop8 sequence The loop8 mitigation for Spectre-BHB only requires a CPU local DSB rather than a systemwide one, which is much more costly. And by the same reasoning as why it is justified to omit the ISB after BPIALL, we can also elide the ISB and rely on the exception return for the context synchronization. Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King (Oracle) --- arch/arm/kernel/entry-armv.S | 5 +++-- arch/arm/kernel/entry-common.S | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 87cb06316aca0..43ab77553e840 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -1131,8 +1131,9 @@ vector_bhb_loop8_\name: 3: W(b) . + 4 subs r0, r0, #1 bne 3b - dsb - isb + dsb nsh + @ isb not needed due to "movs pc, lr" in the vector stub + @ which gives a "context synchronisation". b 2b ENDPROC(vector_bhb_loop8_\name) .previous diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index ad3210e5cb692..7aa3ded4af929 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -164,7 +164,7 @@ ENTRY(vector_bhb_loop8_swi) 1: b 2f 2: subs r8, r8, #1 bne 1b - dsb + dsb nsh isb b 3f ENDPROC(vector_bhb_loop8_swi) -- 2.39.5