From 60da130a8c5ac29bc35870180c35ca04db506e0f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 23 Aug 2022 10:45:54 +0100 Subject: [PATCH] fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names The arm,vexpress,config-bus DT binding restricts the possible (sub)node names. Adjust the current node names, to drop the unneeded address specifier, and make the node names binding compliant. Change-Id: Ic48c6969268c960ce92c8ec3a756ed1d89e61b08 Signed-off-by: Andre Przywara --- fdts/fvp-ve-Cortex-A5x1.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/fdts/fvp-ve-Cortex-A5x1.dts b/fdts/fvp-ve-Cortex-A5x1.dts index 23a6e1382..612b3b2d1 100644 --- a/fdts/fvp-ve-Cortex-A5x1.dts +++ b/fdts/fvp-ve-Cortex-A5x1.dts @@ -77,7 +77,7 @@ }; mcc { - oscclk0: osc@0 { + oscclk0: oscclk0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -86,7 +86,7 @@ clock-output-names = "oscclk0"; }; - oscclk1: osc@1 { + oscclk1: oscclk1 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -95,7 +95,7 @@ clock-output-names = "oscclk1"; }; - osc@2 { + oscclk2 { /* DDR2 */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -104,7 +104,7 @@ clock-output-names = "oscclk2"; }; - oscclk3: osc@3 { + oscclk3: oscclk3 { /* HDLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -113,7 +113,7 @@ clock-output-names = "oscclk3"; }; - osc@4 { + oscclk4 { /* Test chip gate configuration */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -122,7 +122,7 @@ clock-output-names = "oscclk4"; }; - smbclk: osc@5 { + smbclk: oscclk5 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; -- 2.39.5