From 51cfbc7b616f556098bf6715e84b95966d552398 Mon Sep 17 00:00:00 2001 From: Dongwon Kim Date: Thu, 14 Apr 2016 15:37:43 -0700 Subject: [PATCH] drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variations This patch is to correct one thing in this commit: commit a3619efd2076492c74c59303e4b2c91d13faf1b1 Author: Dongwon Kim Date: Wed Mar 16 18:06:13 2016 -0700 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit This reversed bit polarity is actually common for all BXT and APL SoCs. Therefore, revision checking in the original commit should be removed to make the bit set regardless of revision ID of GFX block. Signed-off-by: Dongwon Kim Reviewed-by: Imre Deak Signed-off-by: Imre Deak Link: http://patchwork.freedesktop.org/patch/msgid/1460673463-14453-1-git-send-email-dongwon.kim@intel.com --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 763132d1b63f3..639bf0209c155 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1295,17 +1295,9 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, uint32_t temp; enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); - /* - * Definition of each bit polarity has been changed - * after A1 stepping - */ - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) - temp &= ~PORT_PLL_REF_SEL; - else - temp |= PORT_PLL_REF_SEL; - /* Non-SSC reference */ + temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp |= PORT_PLL_REF_SEL; I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); /* Disable 10 bit clock */ -- 2.39.5