From 4db96de45dd76ff51ac188ef36033500bbc4ec69 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 11 Nov 2022 12:49:38 -0600 Subject: [PATCH] refactor(ti): factor out common board code into common files Signed-off-by: Andrew Davis Change-Id: Ibf7328418c5285a64608b80e7c430a8dee64fb1d --- plat/ti/k3/board/generic/board.mk | 12 ---------- plat/ti/k3/board/generic/include/board_def.h | 21 ------------------ plat/ti/k3/board/j784s4/board.mk | 12 ---------- plat/ti/k3/board/j784s4/include/board_def.h | 21 ------------------ plat/ti/k3/board/lite/board.mk | 12 ---------- plat/ti/k3/board/lite/include/board_def.h | 23 -------------------- plat/ti/k3/include/platform_def.h | 22 ++++++++++++++----- plat/ti/k3/platform.mk | 11 ++++++++++ 8 files changed, 27 insertions(+), 107 deletions(-) diff --git a/plat/ti/k3/board/generic/board.mk b/plat/ti/k3/board/generic/board.mk index ef74cd64c..58c966a8e 100644 --- a/plat/ti/k3/board/generic/board.mk +++ b/plat/ti/k3/board/generic/board.mk @@ -4,21 +4,9 @@ # SPDX-License-Identifier: BSD-3-Clause # -BL32_BASE ?= 0x9e800000 -$(eval $(call add_define,BL32_BASE)) - -PRELOADED_BL33_BASE ?= 0x80080000 -$(eval $(call add_define,PRELOADED_BL33_BASE)) - -K3_HW_CONFIG_BASE ?= 0x82000000 -$(eval $(call add_define,K3_HW_CONFIG_BASE)) - # Define sec_proxy usage as the full prioritized communication scheme K3_SEC_PROXY_LITE := 0 $(eval $(call add_define,K3_SEC_PROXY_LITE)) # System coherency is managed in hardware USE_COHERENT_MEM := 1 - -PLAT_INCLUDES += \ - -Iplat/ti/k3/board/generic/include \ diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h index e118cc3e8..edfa73fda 100644 --- a/plat/ti/k3/board/generic/include/board_def.h +++ b/plat/ti/k3/board/generic/include/board_def.h @@ -15,27 +15,6 @@ #define K3_CLUSTER2_CORE_COUNT U(2) #define K3_CLUSTER3_CORE_COUNT U(2) -/* - * This RAM will be used for the bootloader including code, bss, and stacks. - * It may need to be increased if BL31 grows in size. - * - * The link addresses are determined by SEC_SRAM_BASE + offset. - * When ENABLE_PIE is set, the TF images can be loaded anywhere, so - * SEC_SRAM_BASE is really arbitrary. - * - * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that - * it matches to the physical address where BL31 is loaded, that is, - * SEC_SRAM_BASE should be the base address of the RAM region. - * - * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is - * defined as default for our platform. - */ -#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ -#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */ - -#define PLAT_MAX_OFF_STATE U(2) -#define PLAT_MAX_RET_STATE U(1) - #define PLAT_PROC_START_ID U(32) #define PLAT_PROC_DEVICE_START_ID U(202) #define PLAT_CLUSTER_DEVICE_START_ID U(198) diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk index 68ba1b527..21d41512d 100644 --- a/plat/ti/k3/board/j784s4/board.mk +++ b/plat/ti/k3/board/j784s4/board.mk @@ -4,15 +4,6 @@ # SPDX-License-Identifier: BSD-3-Clause # -BL32_BASE ?= 0x9e800000 -$(eval $(call add_define,BL32_BASE)) - -PRELOADED_BL33_BASE ?= 0x80080000 -$(eval $(call add_define,PRELOADED_BL33_BASE)) - -K3_HW_CONFIG_BASE ?= 0x82000000 -$(eval $(call add_define,K3_HW_CONFIG_BASE)) - # Define sec_proxy usage as the full prioritized communication scheme K3_SEC_PROXY_LITE := 0 $(eval $(call add_define,K3_SEC_PROXY_LITE)) @@ -27,6 +18,3 @@ $(eval $(call add_define,K3_EXCLUSIVE_SNOOP_DELAY)) # System coherency is managed in hardware USE_COHERENT_MEM := 1 - -PLAT_INCLUDES += \ - -Iplat/ti/k3/board/j784s4/include \ diff --git a/plat/ti/k3/board/j784s4/include/board_def.h b/plat/ti/k3/board/j784s4/include/board_def.h index 5683fc0b1..c8179992a 100644 --- a/plat/ti/k3/board/j784s4/include/board_def.h +++ b/plat/ti/k3/board/j784s4/include/board_def.h @@ -14,29 +14,8 @@ #define K3_CLUSTER1_CORE_COUNT U(4) #define K3_CLUSTER2_CORE_COUNT U(0) #define K3_CLUSTER3_CORE_COUNT U(0) -/* - * This RAM will be used for the bootloader including code, bss, and stacks. - * It may need to be increased if BL31 grows in size. - * - * The link addresses are determined by SEC_SRAM_BASE + offset. - * When ENABLE_PIE is set, the TF images can be loaded anywhere, so - * SEC_SRAM_BASE is really arbitrary. - * - * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that - * it matches to the physical address where BL31 is loaded, that is, - * SEC_SRAM_BASE should be the base address of the RAM region. - * - * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is - * defined as default for our platform. - */ -#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ -#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */ - -#define PLAT_MAX_OFF_STATE U(2) -#define PLAT_MAX_RET_STATE U(1) #define PLAT_PROC_START_ID U(32) - #define PLAT_PROC_DEVICE_START_ID U(202) #define PLAT_CLUSTER_DEVICE_START_ID U(198) #define PLAT_BOARD_DEVICE_ID U(157) diff --git a/plat/ti/k3/board/lite/board.mk b/plat/ti/k3/board/lite/board.mk index 76246be47..2fa09ad36 100644 --- a/plat/ti/k3/board/lite/board.mk +++ b/plat/ti/k3/board/lite/board.mk @@ -4,21 +4,9 @@ # SPDX-License-Identifier: BSD-3-Clause # -BL32_BASE ?= 0x9e800000 -$(eval $(call add_define,BL32_BASE)) - -PRELOADED_BL33_BASE ?= 0x80080000 -$(eval $(call add_define,PRELOADED_BL33_BASE)) - -K3_HW_CONFIG_BASE ?= 0x82000000 -$(eval $(call add_define,K3_HW_CONFIG_BASE)) - # Define sec_proxy usage as the lite version K3_SEC_PROXY_LITE := 1 $(eval $(call add_define,K3_SEC_PROXY_LITE)) # We dont have system level coherency capability USE_COHERENT_MEM := 0 - -PLAT_INCLUDES += \ - -Iplat/ti/k3/board/lite/include \ diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h index b300c0833..f523198fd 100644 --- a/plat/ti/k3/board/lite/include/board_def.h +++ b/plat/ti/k3/board/lite/include/board_def.h @@ -15,29 +15,6 @@ #define K3_CLUSTER2_CORE_COUNT U(0) #define K3_CLUSTER3_CORE_COUNT U(0) -/* - * This RAM will be used for the bootloader including code, bss, and stacks. - * It may need to be increased if BL31 grows in size. - * Current computation assumes data structures necessary for GIC and ARM for - * a single cluster of 4 processor. - * - * The link addresses are determined by SEC_SRAM_BASE + offset. - * When ENABLE_PIE is set, the TF images can be loaded anywhere, so - * SEC_SRAM_BASE is really arbitrary. - * - * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that - * it matches to the physical address where BL31 is loaded, that is, - * SEC_SRAM_BASE should be the base address of the RAM region. - * - * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is - * defined as default for our platform. - */ -#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ -#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */ - -#define PLAT_MAX_OFF_STATE U(2) -#define PLAT_MAX_RET_STATE U(1) - #define PLAT_PROC_START_ID U(32) #define PLAT_PROC_DEVICE_START_ID U(135) #define PLAT_CLUSTER_DEVICE_START_ID U(134) diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h index 81a383a72..ae3775a27 100644 --- a/plat/ti/k3/include/platform_def.h +++ b/plat/ti/k3/include/platform_def.h @@ -38,21 +38,31 @@ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) /******************************************************************************* * Memory layout constants ******************************************************************************/ /* - * ARM-TF lives in SRAM, partition it here + * This RAM will be used for the bootloader including code, bss, and stacks. + * It may need to be increased if BL31 grows in size. * - * BL3-1 specific defines. + * The link addresses are determined by BL31_BASE + offset. + * When ENABLE_PIE is set, the TF images can be loaded anywhere, so + * BL31_BASE is really arbitrary. * - * Put BL3-1 at the base of the Trusted SRAM. + * When ENABLE_PIE is unset, BL31_BASE should be chosen so that + * it matches to the physical address where BL31 is loaded, that is, + * BL31_BASE should be the base address of the RAM region. + * + * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is + * defined as default for our platform. */ -#define BL31_BASE SEC_SRAM_BASE -#define BL31_SIZE SEC_SRAM_SIZE -#define BL31_LIMIT (BL31_BASE + BL31_SIZE) +#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */ +#define BL31_SIZE UL(0x00020000) /* 128k */ +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) /* * Defines the maximum number of translation tables that are allocated by the diff --git a/plat/ti/k3/platform.mk b/plat/ti/k3/platform.mk index 2de21aa7b..bce9ef176 100644 --- a/plat/ti/k3/platform.mk +++ b/plat/ti/k3/platform.mk @@ -10,5 +10,16 @@ TARGET_BOARD ?= generic include ${PLAT_PATH}/common/plat_common.mk include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk +BL32_BASE ?= 0x9e800000 +$(eval $(call add_define,BL32_BASE)) + +PRELOADED_BL33_BASE ?= 0x80080000 +$(eval $(call add_define,PRELOADED_BL33_BASE)) + +K3_HW_CONFIG_BASE ?= 0x82000000 +$(eval $(call add_define,K3_HW_CONFIG_BASE)) + +PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include + # modify BUILD_PLAT to point to board specific build directory BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE} -- 2.39.5