From 366e33615c5acfd896d3ac18d24f83ef3d24b894 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 12 May 2020 15:45:39 -0500 Subject: [PATCH] spi: dt-bindings: sifive: Add missing 2nd register region The 'reg' description and example have a 2nd register region for memory mapped flash, but the schema says there is only 1 region. Fix this. Cc: Palmer Dabbelt Cc: linux-spi@vger.kernel.org Cc: linux-riscv@lists.infradead.org Acked-by: Mark Brown Acked-by: Paul Walmsley Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/spi/spi-sifive.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 28040598bfaef..fb583e57c1f23 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -32,11 +32,10 @@ properties: https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi reg: - maxItems: 1 - - description: - Physical base address and size of SPI registers map - A second (optional) range can indicate memory mapped flash + minItems: 1 + items: + - description: SPI registers region + - description: Memory mapped flash region interrupts: maxItems: 1 -- 2.39.5