From 34b3cbcb6c794837e9a2c3ac27619db9b5279d00 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Thu, 18 Sep 2014 14:47:13 -0700 Subject: [PATCH] MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs. Since systems using CPS must also have a GIC, which is responsible for routing all external interrupts and can map them to any hardware interrupt vector, enable the remaining vectors. The two software interrupt vectors are left disabled since they are not used with CPS. Signed-off-by: Andrew Bresticker Reviewed-by: Qais Yousef Tested-by: Qais Yousef Cc: Thomas Gleixner Cc: Jason Cooper Cc: Andrew Bresticker Cc: Jeffrey Deans Cc: Markos Chandras Cc: Paul Burton Cc: Qais Yousef Cc: Jonas Gorski Cc: John Crispin Cc: David Daney Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7803/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index e6e16a1d4add0..cd20acad7f177 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -273,8 +273,8 @@ static void cps_init_secondary(void) if (cpu_has_mipsmt) dmt(); - change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | - STATUSF_IP6 | STATUSF_IP7); + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | + STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); } static void cps_smp_finish(void) -- 2.39.5