2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/bootmem.h>
17 #include <linux/msi.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/of_platform.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
30 struct fsl_msi_feature {
35 struct fsl_msi_cascade_data {
36 struct fsl_msi *msi_data;
40 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
42 return in_be32(base + (reg >> 2));
46 * We do not need this actually. The MSIR register has been read once
47 * in the cascade interrupt. So, this MSI interrupt has been acked
49 static void fsl_msi_end_irq(unsigned int virq)
53 static struct irq_chip fsl_msi_chip = {
55 .unmask = unmask_msi_irq,
56 .ack = fsl_msi_end_irq,
60 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
63 struct fsl_msi *msi_data = h->host_data;
64 struct irq_chip *chip = &fsl_msi_chip;
66 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
68 set_irq_chip_data(virq, msi_data);
69 set_irq_chip_and_handler(virq, chip, handle_edge_irq);
74 static struct irq_host_ops fsl_msi_host_ops = {
75 .map = fsl_msi_host_map,
78 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
82 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
83 msi_data->irqhost->of_node);
87 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
89 msi_bitmap_free(&msi_data->bitmap);
96 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
98 if (type == PCI_CAP_ID_MSIX)
99 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
104 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
106 struct msi_desc *entry;
107 struct fsl_msi *msi_data;
109 list_for_each_entry(entry, &pdev->msi_list, list) {
110 if (entry->irq == NO_IRQ)
112 msi_data = get_irq_data(entry->irq);
113 set_irq_msi(entry->irq, NULL);
114 msi_bitmap_free_hwirqs(&msi_data->bitmap,
115 virq_to_hw(entry->irq), 1);
116 irq_dispose_mapping(entry->irq);
122 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
124 struct fsl_msi *fsl_msi_data)
126 struct fsl_msi *msi_data = fsl_msi_data;
127 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
130 pci_bus_read_config_dword(hose->bus,
131 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
133 msg->address_lo = msi_data->msi_addr_lo + base;
134 msg->address_hi = msi_data->msi_addr_hi;
137 pr_debug("%s: allocated srs: %d, ibs: %d\n",
138 __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
141 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
143 int rc, hwirq = -ENOMEM;
145 struct msi_desc *entry;
147 struct fsl_msi *msi_data;
149 list_for_each_entry(entry, &pdev->msi_list, list) {
150 list_for_each_entry(msi_data, &msi_head, list) {
151 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
158 pr_debug("%s: fail allocating msi interrupt\n",
163 virq = irq_create_mapping(msi_data->irqhost, hwirq);
165 if (virq == NO_IRQ) {
166 pr_debug("%s: fail mapping hwirq 0x%x\n",
168 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
172 set_irq_data(virq, msi_data);
173 set_irq_msi(virq, entry);
175 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
176 write_msi_msg(virq, &msg);
181 /* free by the caller of this function */
185 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
187 unsigned int cascade_irq;
188 struct fsl_msi *msi_data;
193 struct fsl_msi_cascade_data *cascade_data;
195 cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
196 msi_data = cascade_data->msi_data;
198 raw_spin_lock(&desc->lock);
199 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
200 if (desc->chip->mask_ack)
201 desc->chip->mask_ack(irq);
203 desc->chip->mask(irq);
204 desc->chip->ack(irq);
208 if (unlikely(desc->status & IRQ_INPROGRESS))
211 msir_index = cascade_data->index;
213 if (msir_index >= NR_MSI_REG)
214 cascade_irq = NO_IRQ;
216 desc->status |= IRQ_INPROGRESS;
217 switch (msi_data->feature & FSL_PIC_IP_MASK) {
218 case FSL_PIC_IP_MPIC:
219 msir_value = fsl_msi_read(msi_data->msi_regs,
222 case FSL_PIC_IP_IPIC:
223 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
228 intr_index = ffs(msir_value) - 1;
230 cascade_irq = irq_linear_revmap(msi_data->irqhost,
231 msir_index * IRQS_PER_MSI_REG +
232 intr_index + have_shift);
233 if (cascade_irq != NO_IRQ)
234 generic_handle_irq(cascade_irq);
235 have_shift += intr_index + 1;
236 msir_value = msir_value >> (intr_index + 1);
238 desc->status &= ~IRQ_INPROGRESS;
240 switch (msi_data->feature & FSL_PIC_IP_MASK) {
241 case FSL_PIC_IP_MPIC:
242 desc->chip->eoi(irq);
244 case FSL_PIC_IP_IPIC:
245 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
246 desc->chip->unmask(irq);
250 raw_spin_unlock(&desc->lock);
253 static int __devinit fsl_of_msi_probe(struct of_device *dev,
254 const struct of_device_id *match)
262 struct fsl_msi_feature *features = match->data;
263 struct fsl_msi_cascade_data *cascade_data = NULL;
265 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
267 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
269 dev_err(&dev->dev, "No memory for MSI structure\n");
274 msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
275 NR_MSI_IRQS, &fsl_msi_host_ops, 0);
277 if (msi->irqhost == NULL) {
278 dev_err(&dev->dev, "No memory for MSI irqhost\n");
283 /* Get the MSI reg base */
284 err = of_address_to_resource(dev->node, 0, &res);
286 dev_err(&dev->dev, "%s resource error!\n",
287 dev->node->full_name);
291 msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
292 if (!msi->msi_regs) {
293 dev_err(&dev->dev, "ioremap problem failed\n");
297 msi->feature = features->fsl_pic_ip;
299 msi->irqhost->host_data = msi;
301 msi->msi_addr_hi = 0x0;
302 msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
304 rc = fsl_msi_init_allocator(msi);
306 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
310 p = of_get_property(dev->node, "interrupts", &count);
312 dev_err(&dev->dev, "no interrupts property found on %s\n",
313 dev->node->full_name);
317 if (count % 8 != 0) {
318 dev_err(&dev->dev, "Malformed interrupts property on %s\n",
319 dev->node->full_name);
324 count /= sizeof(u32);
325 for (i = 0; i < count / 2; i++) {
328 virt_msir = irq_of_parse_and_map(dev->node, i);
329 if (virt_msir != NO_IRQ) {
330 cascade_data = kzalloc(
331 sizeof(struct fsl_msi_cascade_data),
335 "No memory for MSI cascade data\n");
339 cascade_data->index = i;
340 cascade_data->msi_data = msi;
341 set_irq_data(virt_msir, (void *)cascade_data);
342 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
346 list_add_tail(&msi->list, &msi_head);
348 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
349 if (!ppc_md.setup_msi_irqs) {
350 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
351 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
352 ppc_md.msi_check_device = fsl_msi_check_device;
353 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
354 dev_err(&dev->dev, "Different MSI driver already installed!\n");
364 static const struct fsl_msi_feature mpic_msi_feature = {
365 .fsl_pic_ip = FSL_PIC_IP_MPIC,
366 .msiir_offset = 0x140,
369 static const struct fsl_msi_feature ipic_msi_feature = {
370 .fsl_pic_ip = FSL_PIC_IP_IPIC,
371 .msiir_offset = 0x38,
374 static const struct of_device_id fsl_of_msi_ids[] = {
376 .compatible = "fsl,mpic-msi",
377 .data = (void *)&mpic_msi_feature,
380 .compatible = "fsl,ipic-msi",
381 .data = (void *)&ipic_msi_feature,
386 static struct of_platform_driver fsl_of_msi_driver = {
388 .match_table = fsl_of_msi_ids,
389 .probe = fsl_of_msi_probe,
392 static __init int fsl_of_msi_init(void)
394 return of_register_platform_driver(&fsl_of_msi_driver);
397 subsys_initcall(fsl_of_msi_init);