]> git.baikalelectronics.ru Git - kernel.git/commit
bpf, riscv: Enable zext optimization for more RV64G ALU ops
authorLuke Nelson <lukenels@cs.washington.edu>
Fri, 5 Jul 2019 00:18:02 +0000 (17:18 -0700)
committerDaniel Borkmann <daniel@iogearbox.net>
Fri, 5 Jul 2019 21:55:41 +0000 (23:55 +0200)
commit743fa8b4a741ec3a12214a43008bedd50886f827
tree77cbab40bb36d28213a9cfc0d7a4252865f512ff
parent4f34379a7566b0bf895ced6757ea9789284f939d
bpf, riscv: Enable zext optimization for more RV64G ALU ops

Commit 0c6a86e89153 ("riscv: bpf: eliminate zero extension code-gen")
added the new zero-extension optimization for some BPF ALU operations.

Since then, bugs in the JIT that have been fixed in the bpf tree require
this optimization to be added to other operations: commit 1f3f0b9465ba
("bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh"),
and commit ce91727fff6c ("bpf, riscv: clear target register high 32-bits
for and/or/xor on ALU32").

Now that these have been merged to bpf-next, the zext optimization can
be enabled for the fixed operations.

Signed-off-by: Luke Nelson <luke.r.nels@gmail.com>
Cc: Song Liu <liu.song.a23@gmail.com>
Cc: Jiong Wang <jiong.wang@netronome.com>
Cc: Xi Wang <xi.wang@gmail.com>
Acked-by: Björn Töpel <bjorn.topel@gmail.com>
Acked-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
arch/riscv/net/bpf_jit_comp.c