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1 /*

3 *

4 * Permission is hereby granted, free of charge, to any person obtaining a

5 * copy of this software and associated documentation files (the "Software"),

6 * to deal in the Software without restriction, including without limitation

7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

8 * and/or sell copies of the Software, and to permit persons to whom the

9 * Software is furnished to do so, subject to the following conditions:

10 *

11 * The above copyright notice and this permission notice (including the next

12 * paragraph) shall be included in all copies or substantial portions of the

13 * Software.

14 *

15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

21 * IN THE SOFTWARE.

22 *

23 */

25 #ifndef _INTEL_DEVICE_INFO_H_

26 #define _INTEL_DEVICE_INFO_H_

28 #include <uapi/drm/i915_drm.h>

30 #include "display/intel_display.h"

32 #include "gt/intel_engine_types.h"

33 #include "gt/intel_context_types.h"

34 #include "gt/intel_sseu.h"

36 struct drm_printer;

37 struct drm_i915_private;

39 /* Keep in gen based order, and chronological order within a gen */

40 enum intel_platform {

41 INTEL_PLATFORM_UNINITIALIZED = 0,

42 /* gen2 */

43 INTEL_I830,

44 INTEL_I845G,

45 INTEL_I85X,

46 INTEL_I865G,

47 /* gen3 */

48 INTEL_I915G,

49 INTEL_I915GM,

50 INTEL_I945G,

51 INTEL_I945GM,

52 INTEL_G33,

53 INTEL_PINEVIEW,

54 /* gen4 */

55 INTEL_I965G,

56 INTEL_I965GM,

57 INTEL_G45,

58 INTEL_GM45,

59 /* gen5 */

60 INTEL_IRONLAKE,

61 /* gen6 */

62 INTEL_SANDYBRIDGE,

63 /* gen7 */

64 INTEL_IVYBRIDGE,

65 INTEL_VALLEYVIEW,

66 INTEL_HASWELL,

67 /* gen8 */

68 INTEL_BROADWELL,

69 INTEL_CHERRYVIEW,

70 /* gen9 */

71 INTEL_SKYLAKE,

72 INTEL_BROXTON,

73 INTEL_KABYLAKE,

74 INTEL_GEMINILAKE,

75 INTEL_COFFEELAKE,

76 /* gen10 */

77 INTEL_CANNONLAKE,

78 /* gen11 */

79 INTEL_ICELAKE,

80 INTEL_ELKHARTLAKE,

81 /* gen12 */

82 INTEL_TIGERLAKE,

83 INTEL_MAX_PLATFORMS

84 };

86 /*

87 * Subplatform bits share the same namespace per parent platform. In other words

88 * it is fine for the same bit to be used on multiple parent platforms.

89 */

91 #define INTEL_SUBPLATFORM_BITS (3)

93 /* HSW/BDW/SKL/KBL/CFL */

94 #define INTEL_SUBPLATFORM_ULT (0)

95 #define INTEL_SUBPLATFORM_ULX (1)

97 /* CNL/ICL */

98 #define INTEL_SUBPLATFORM_PORTF (0)

100 enum intel_ppgtt_type {

101 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,

102 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,

103 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,

104 };

105

106 #define DEV_INFO_FOR_EACH_FLAG(func) \

107 func(is_mobile); \

108 func(is_lp); \

109 func(require_force_probe); \

110 /* Keep has_* in alphabetical order */ \

111 func(has_64bit_reloc); \

112 func(gpu_reset_clobbers_display); \

113 func(has_reset_engine); \

114 func(has_fpga_dbg); \

115 func(has_guc); \

116 func(has_l3_dpf); \

117 func(has_llc); \

118 func(has_logical_ring_contexts); \

119 func(has_logical_ring_elsq); \

120 func(has_logical_ring_preemption); \

121 func(has_pooled_eu); \

122 func(has_rc6); \

123 func(has_rc6p); \

124 func(has_rps); \

125 func(has_runtime_pm); \

126 func(has_snoop); \

127 func(has_coherent_ggtt); \

128 func(unfenced_needs_alignment); \

129 func(hws_needs_physical);

130

131 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \

132 /* Keep in alphabetical order */ \

133 func(cursor_needs_physical); \

134 func(has_csr); \

135 func(has_ddi); \

136 func(has_dp_mst); \

137 func(has_fbc); \

138 func(has_gmch); \

139 func(has_hotplug); \

140 func(has_ipc); \

141 func(has_overlay); \

142 func(has_psr); \

143 func(overlay_needs_physical); \

144 func(supports_tv);

145

146 struct intel_device_info {

147 u16 gen_mask;

148

149 u8 gen;

150 u8 gt; /* GT number, 0 if undefined */

151 intel_engine_mask_t engine_mask; /* Engines supported by the HW */

152

153 enum intel_platform platform;

154

155 enum intel_ppgtt_type ppgtt_type;

156 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */

157

158 unsigned int page_sizes; /* page sizes supported by the HW */

159

160 u32 display_mmio_offset;

161

162 u8 num_pipes;

163

164 #define DEFINE_FLAG(name) u8 name:1

165 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);

166 #undef DEFINE_FLAG

167

168 struct {

169 #define DEFINE_FLAG(name) u8 name:1

170 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);

171 #undef DEFINE_FLAG

172 } display;

173

174 u16 ddb_size; /* in blocks */

175

176 /* Register offsets for the various display pipes and transcoders */

177 int pipe_offsets[I915_MAX_TRANSCODERS];

178 int trans_offsets[I915_MAX_TRANSCODERS];

179 int cursor_offsets[I915_MAX_PIPES];

180

181 struct color_luts {

182 u32 degamma_lut_size;

183 u32 gamma_lut_size;

184 u32 degamma_lut_tests;

185 u32 gamma_lut_tests;

186 } color;

187 };

188

189 struct intel_runtime_info {

190 /*

191 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into

192 * into single runtime conditionals, and also to provide groundwork

193 * for future per platform, or per SKU build optimizations.

194 *

195 * Array can be extended when necessary if the corresponding

196 * BUILD_BUG_ON is hit.

197 */

198 u32 platform_mask[2];

199

200 u16 device_id;

201

202 u8 num_sprites[I915_MAX_PIPES];

203 u8 num_scalers[I915_MAX_PIPES];

204

205 u8 num_engines;

206

207 /* Slice/subslice/EU info */

208 struct sseu_dev_info sseu;

209

210 u32 cs_timestamp_frequency_khz;

211

212 /* Media engine access to SFC per instance */

213 u8 vdbox_sfc_access;

214 };

215

216 struct intel_driver_caps {

217 unsigned int scheduler;

218 bool has_logical_contexts:1;

219 };

220

221 const char *intel_platform_name(enum intel_platform platform);

222

223 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);

224 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);

225 void intel_device_info_dump_flags(const struct intel_device_info *info,

226 struct drm_printer *p);

227 void intel_device_info_dump_runtime(const struct intel_runtime_info *info,

228 struct drm_printer *p);

229 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,

230 struct drm_printer *p);

231

232 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);

233

234 void intel_driver_caps_print(const struct intel_driver_caps *caps,

235 struct drm_printer *p);

236

237 #endif