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(parent: be79e39) | patch
x86: Add TSX Force Abort CPUID/MSR
authorPeter Zijlstra (Intel) <peterz@infradead.org>
Tue, 5 Mar 2019 21:23:17 +0000 (22:23 +0100)
committerThomas Gleixner <tglx@linutronix.de>
Wed, 6 Mar 2019 08:25:41 +0000 (09:25 +0100)
commit1d4a2b053581305d587179442eee122a924f2d89
treee61af1fcb70735394b1269070d5a763c52cf604ctree | snapshot
parentbe79e399dd4c7eba587495e26e808fbea0b90155commit | diff
x86: Add TSX Force Abort CPUID/MSR

Skylake systems will receive a microcode update to address a TSX
errata. This microcode will (by default) clobber PMC3 when TSX
instructions are (speculatively or not) executed.

It also provides an MSR to cause all TSX transaction to abort and
preserve PMC3.

Add the CPUID enumeration and MSR definition.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/include/asm/cpufeatures.h diff | blob | history
arch/x86/include/asm/msr-index.h diff | blob | history
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