Matthew Auld [Wed, 16 Jun 2021 15:24:56 +0000 (16:24 +0100)]
drm/i915/ttm: add i915_sg_from_buddy_resource
We need to be able to build an sg table from our list of buddy blocks,
so that we can later plug this into our ttm backend, and replace our use
of the range manager.
Matthew Auld [Wed, 16 Jun 2021 15:24:55 +0000 (16:24 +0100)]
drm/i915/ttm: add ttm_buddy_man
Add back our standalone i915_buddy allocator and integrate it into a
ttm_resource_manager. This will plug into our ttm backend for managing
device local-memory in the next couple of patches.
v2(Thomas):
- Return -ENOSPC from the buddy; ttm expects this in order to
trigger eviction
- Drop the unnecessary inline
- bo->page_alignment is in page units
Thomas Hellström [Thu, 10 Jun 2021 14:35:25 +0000 (16:35 +0200)]
drm/i915: Simplify userptr locking
Use an rwlock instead of spinlock for the global notifier lock
to reduce risk of contention in execbuf.
Protect object state with the object lock whenever possible rather
than with the global notifier lock
Don't take an explicit page_ref in userptr_submit_init() but rather
call get_pages() after obtaining the page list so that
get_pages() holds the page_ref. This means we don't need to call
userptr_submit_fini(), which is needed to avoid awkward locking
in our upcoming VM_BIND code.
Joonas Lahtinen [Mon, 14 Jun 2021 09:24:24 +0000 (12:24 +0300)]
Merge tag 'topic/i915-ttm-2021-06-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-intel-gt-next
drm-misc and drm-intel pull request for topic/i915-ttm:
- Convert i915 lmem handling to ttm.
- Add a patch to temporarily add a driver_private member to vma_node.
- Use this to allow mixed object mmap handling for i915.
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to look at vma_node->driver_private
to fetch the bo, if it's NULL, we assume i915's normal mmap_offset uapi
is used.
This is the easiest way to achieve compatibility without changing ttm's
semantics.
Thomas Hellström [Thu, 10 Jun 2021 07:01:50 +0000 (09:01 +0200)]
drm/i915/lmem: Verify checks for lmem residency
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Thomas Hellström [Thu, 10 Jun 2021 07:01:49 +0000 (09:01 +0200)]
drm/i915/ttm: Introduce a TTM i915 gem object backend
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM objects) is not
visible to i915 GEM yet. The plan is to move the i915 gem system region
over to the TTM system memory type in upcoming patches.
We set up GPU bindings directly both from LMEM and from the system region,
as there is no need to use the legacy TTM_TT memory type. We reserve
that for future porting of GGTT bindings to TTM.
Dave Airlie [Fri, 11 Jun 2021 04:19:06 +0000 (14:19 +1000)]
Merge tag 'exynos-drm-next-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Two cleanups
- These patches make Exynos DRM driver to use pm_runtime_resume_and_get()
function instead of m_runtime_get_sync() to deal with usage counter.
pm_runtime_get_sync() increases the usage counter even when it failed,
which could make callers to forget to decrease the usage counter.
pm_runtime_resume_and_get() decreases the usage counter regardless of
whether it failed or not.
Dave Airlie [Fri, 11 Jun 2021 03:34:42 +0000 (13:34 +1000)]
Merge tag 'drm-intel-gt-next-2021-06-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
UAPI Changes:
- Disable mmap ioctl for gen12+ (excl. TGL-LP)
- Start enabling HuC loading by default for upcoming Gen12+
platforms (excludes TGL and RKL)
Core Changes:
- Backmerge of drm-next
Driver Changes:
- Revert "i915: use io_mapping_map_user" (Eero, Matt A)
- Initialize the TTM device and memory managers (Thomas)
- Major rework to the GuC submission backend to prepare
for enabling on new platforms (Michal Wa., Daniele,
Matt B, Rodrigo)
- Fix i915_sg_page_sizes to record dma segments rather
than physical pages (Thomas)
- Locking rework to prep for TTM conversion (Thomas)
- Replace IS_GEN and friends with GRAPHICS_VER (Lucas)
- Use DEVICE_ATTR_RO macro (Yue)
- Static code checker fixes (Zhihao)
Dave Airlie [Fri, 11 Jun 2021 02:50:47 +0000 (12:50 +1000)]
Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next
- remove redundant NULL checks by various people
- fix sparse checker warnings from Marc
- expose more GPU ID values to userspace from Christian
- add HWDB entry for GPU found on i.MX8MP from Sascha
- rework of the linear window calculation to better deal with
systems with large regions of reserved RAM
Inki Dae [Tue, 25 May 2021 10:51:39 +0000 (19:51 +0900)]
drm/exynos: use pm_runtime_resume_and_get()
Use pm_runtime_resume_and_get() instead of pm_runtime_get_sync()
to deal with usage counter. pm_runtime_get_sync() increases the
usage counter even when it failed, which makes callers to forget
to decrease the usage counter and resulted in reference leak.
pm_runtime_resume_and_get() function decreases the usage counter
when it failed internally so it can avoid the reference leak.
Changelog v1:
- Fix an build error reported by kernel test robot of Intel.
Signed-off-by: Inki Dae <inki.dae@samsung.com> Reported-by: kernel test robot <lkp@intel.com>
Tian Tao [Mon, 24 May 2021 12:07:57 +0000 (20:07 +0800)]
drm/exynos: Use pm_runtime_resume_and_get() to replace open coding
use pm_runtime_resume_and_get() to replace pm_runtime_get_sync and
pm_runtime_put_noidle to avoid continuing to increase the refcount
when pm_runtime_get_sync fails.
Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Alex Deucher [Mon, 7 Jun 2021 20:19:46 +0000 (16:19 -0400)]
drm/amdgpu/vcn: drop gfxoff control for VCN2+
Drop disabling of gfxoff during VCN use. This allows gfxoff
to kick in and potentially save power if the user is not using
gfx for color space conversion or scaling.
VCN1.0 had a bug which prevented it from working properly with
gfxoff, so we disabled it while using VCN. That said, most apps
today use gfx for scaling and color space conversion rather than
overlay planes so it was generally in use anyway. This was fixed
on VCN2+, but since we mostly use gfx for color space conversion
and scaling and rapidly powering up/down gfx can negate the
advantages of gfxoff, we left gfxoff disabled. As more
applications use overlay planes for color space conversion
and scaling, this starts to be a win, so go ahead and leave
gfxoff enabled.
Note that VCN1.0 uses vcn_v1_0_idle_work_handler() and
vcn_v1_0_ring_begin_use() so they are not affected by this
patch.
Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* ttm: Make struct ttm_resource the base of all managers + changes
in all users of TTM; Add a generic memcpy for page-based iomem; Remove
use of VM_MIXEDMAP; Cleanups
Driver Changes:
* drm/bridge: Add TI SN65DSI83 and SN65DSI84 + DT bindings
* drm/hyperv: Add DRM driver for HyperV graphics output
* drm/msm: Fix module dependencies
* drm/panel: KD53T133: Support rotation
* drm/pl111: Fix module dependencies
* drm/qxl: Fixes
* drm/stm: Cleanups
* drm/sun4i: Be explicit about format modifiers
* drm/vc4: Use struct gpio_desc; Cleanups
* drm/vgem: Cleanups
* drm/vmwgfx: Use ttm_bo_move_null() if there's nothing to copy
John Harrison [Thu, 3 Jun 2021 16:48:12 +0000 (09:48 -0700)]
drm/i915/uc: Use platform specific defaults for GuC/HuC enabling
The meaning of 'default' for the enable_guc module parameter has been
updated to accurately reflect what is supported on current platforms.
So start using the defaults instead of forcing everything off.
Although, note that right now, the default is for everything to be off
anyway. So this is not a change for current platforms.
drm/i915/adl_p: Same slices mask is not same Dbuf state
We currently treat same slice mask as a same DBuf state and skip
updating the Dbuf slices, if we detect that.
This is wrong as if we have a multi to single pipe change or
vice versa, that would be treated as a same Dbuf state and thus
no changes required, so we don't get Mbus updated, causing issues.
Solution: check also mbus_join, in addition to slices mask.
Colin Ian King [Tue, 8 Jun 2021 16:13:13 +0000 (17:13 +0100)]
drm: qxl: ensure surf.data is ininitialized
The object surf is not fully initialized and the uninitialized
field surf.data is being copied by the call to qxl_bo_create
via the call to qxl_gem_object_create. Set surf.data to zero
to ensure garbage data from the stack is not being copied.
Ville Syrjälä [Tue, 8 Jun 2021 08:54:15 +0000 (11:54 +0300)]
drm/i915: Disable PSR around cdclk changes
AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.
Gwan-gyeong Mun [Tue, 8 Jun 2021 08:54:14 +0000 (11:54 +0300)]
drm/i915/display: Introduce new intel_psr_pause/resume function
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
- Remove unneeded changes around the intel_psr_enable().
- Add intel_psr_post_exit() which processes waiting until PSR is idle
and WA for SelectiveFetch.
v3: Address Jose's review comment.
- Rename intel_psr_post_exit() to intel_psr_wait_exit_locked().
- Move WA_1408330847 to intel_psr_disable_locked()
- If the PSR is paused by an explicit intel_psr_paused() call, make the
intel_psr_flush() not to activate PSR.
v4: Address Jose's review comment.
- In order to avoid the scenario of PSR is not active but there is a
scheduled psr->work, it changes the check routine of intel_psr_pause()
for PSR's enablement from "psr->active" to "psr->enable".
Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210608085415.515342-1-gwan-gyeong.mun@intel.com
Marek Vasut [Mon, 7 Jun 2021 17:24:57 +0000 (19:24 +0200)]
drm/stm: Remove usage of drm_display_mode_to_videomode()
There is not much value in the extra conversion step, the calculations
required for the LTDC IP are different than what is used in the
drm_display_mode_to_videomode(), so just do the right ones in the LTDC
driver right away.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Antonio Borneo <antonio.borneo@foss.st.com> Cc: Benjamin Gaignard <benjamin.gaignard@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Philippe Cornu <philippe.cornu@foss.st.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Vincent Abriou <vincent.abriou@foss.st.com> Cc: Yannick Fertre <yannick.fertre@foss.st.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com
To: dri-devel@lists.freedesktop.org Tested-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210607172457.14471-1-marex@denx.de
Po-Ting Chen [Wed, 5 May 2021 12:46:36 +0000 (20:46 +0800)]
drm/amd/display: Add swizzle visual confirm mode
[Why]
To support a new visual confirm mode: swizzle to show the specific
color at the screen border according to different surface swizzle mode.
Currently we only support the Linear mode with red color.
Signed-off-by: Po-Ting Chen <robin.chen@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: force CP to DESIRED when removing display
[WHY]
- Commit from userspace could cause link stream to disable and hdcp
auth to reset when the HDCP has already been enabled at the moment.
CP should fall back to DESIRED from ENABLED in such cases.
- This change was previously reverted due to a regression caused, which
has now been cleared.
[HOW]
In hdcp display removal, change CP to DESIRED if at the moment CP
is ENABLED before the auth reset and removal of linked list element.
Signed-off-by: Dingchen (David) Zhang <dingchen.zhang@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Wed, 26 May 2021 19:22:51 +0000 (15:22 -0400)]
drm/amd/display: Updates for ODM Transition Test
[Why]
There is an assert in cases where transition from ODM 2:1
to ODM 1:1 (bypass)
[How]
Remove assert since this case is now valid.
Update diags tests for ODM transitions.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roy Chan [Thu, 20 May 2021 20:20:39 +0000 (16:20 -0400)]
drm/amd/display: Revert "Disconnect non-DP with no EDID"
[Why]
Found a use case (IPKVM) that DP-VGA active dongle does
not return any EDID and the mentioned commit broke it.
[How]
This reverts "Disconnect non-DP with no EDID"
Signed-off-by: Roy Chan <roy.chan@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fangzhi Zuo [Wed, 26 May 2021 00:39:12 +0000 (20:39 -0400)]
drm/amd/display: Add debugfs entry for dsc passthrough
[Why & How]
Add debugfs entry to force dsc decoding at PCON when DSC capable
external RX is connected. In such case, it is free to test DSC
decoding at external RX or at PCON.
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 22 May 2021 23:45:46 +0000 (19:45 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.68
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vladimir Stempen [Wed, 19 May 2021 17:55:46 +0000 (13:55 -0400)]
drm/amd/display: Release MST resources on switch from MST to SST
[why]
When OS overrides training link training parameters
for MST device to SST mode, MST resources are not
released and leak of the resource may result crash and
incorrect MST discovery during following hot plugs.
[how]
Retaining sink object to be reused by SST link and
releasing MST resources.
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Wed, 19 May 2021 21:32:16 +0000 (17:32 -0400)]
drm/amd/display: Enable PSR Residency for multiple panels
[why]
Allow specifying which panel to take PSR Residency
measurements from.
[how]
Pass panel instance to DMUB through GPINT in the upper
8 bits of the parameter.
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Return last used DRR VTOTAL from DC
[How]
Add call to get the last used VTOTAL from DC
Signed-off-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove unused definition of DMUB SET_CONFIG
[Why & How]
SET_CONFIG transactions with DMUB is not used and removed.
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Fri, 21 May 2021 14:20:25 +0000 (10:20 -0400)]
drm/amd/display: Update scaling settings on modeset
[Why]
We update scaling settings when scaling mode has been changed.
However when changing mode from native resolution the scaling mode previously
set gets ignored.
[How]
Perform scaling settings update on modeset.
Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jimmy Kizito [Wed, 21 Apr 2021 14:34:34 +0000 (10:34 -0400)]
drm/amd/display: Support mappable encoders when transmitting training patterns.
[Why & How]
Add support for transmitting training pattern sequences for links whose
encoders have been dynamically assigned.
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
Add functionality useful for DP equalization phase of link training to
public interface.
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
This change was found to break some high-refresh modes. Reverting
to unblock mainline.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Thu, 6 May 2021 20:11:16 +0000 (16:11 -0400)]
drm/amd/display: Refactor visual confirm
[Why + How]
Visual confirm has no asic-specific logic,
so we can refactor and unify these functions
that are currently spread out across multiple
dcn files.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
This will allow visual confirm to updated independently
of MPCC blending updates.
v2: squash in DCN3.1 fixes
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
JinZe.Xu [Tue, 18 May 2021 06:36:37 +0000 (14:36 +0800)]
drm/amd/display: Control power gating by driver.
[Why]
This disablement would be specific for Nav10 and shouldn’t be propagated to the other programs.
[How]
Power gating is controlled by driver.
Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Tue, 18 May 2021 16:33:12 +0000 (12:33 -0400)]
drm/amd/display: Fix DCN 3.01 DSCCLK validation
[why]
DSCCLK validation is not necessary because DSCCLK is derrived from
DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too.
Doing DSCLK validation in addition to DISPCLK leads to modes being
wrongly rejected when DSCCLK was incorrectly set outside of DML.
[how]
Remove DSCCLK validation because it's implicitly validated under DISPCLK
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Mon, 17 May 2021 19:54:19 +0000 (15:54 -0400)]
drm/amd/display: delay 100ms before restart after failing to read CP_IRQ
[why]
Some DPRX will issue CP_IRQ when user disconnects a display
that has been authenticated.
Since display is being disconnecting dpcd read will fail.
This will cause us to attempt HDCP retry on disconnection.
We are adding a 100ms delay before retry.
So we will only start retry if within 100ms there is no disconnection call
to HDCP module.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Mon, 17 May 2021 22:18:25 +0000 (18:18 -0400)]
drm/amd/display: Enabling PSR support for multiple panels
[why]
Updating PSR interfaces to allow PSR enablement
per eDP panel.
[how]
- Copying PSR command structures to DC
- Changing function interfaces to pass panel instance
- Communicating with DMUB per link instead of assuming
to use a single one
-Iterating through all PSR capable panels when enabling/disabling
all
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jake Wang [Fri, 14 May 2021 19:41:39 +0000 (15:41 -0400)]
drm/amd/display: Trigger full update after DCC on/off
[Why]
During DCC on/off, stutter period is calculated before DCC has fully transitioned.
This results in incorrect stutter period calculation.
[How]
Trigger a full update when DCC changes between on/off.
Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaomeng Hou [Mon, 7 Jun 2021 08:36:41 +0000 (16:36 +0800)]
drm/amd/pm: fix warning reported by kernel test robot
Kernel test robot throws warning ->
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2:
warning: variable 'member_type' is used uninitialized whenever switch
default is taken [-Wsometimes-uninitialized]
default:
^~~~~~~
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47:
note: uninitialized use occurs here
return yellow_carp_get_smu_metrics_data(smu, member_type, value);
^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2:
note: variable 'member_type' is declared here
MetricsMember_t member_type;
^
1 warning generated.
Fix this warning by return errno when the clk type is unsupported.
Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nirmoy Das [Tue, 8 Jun 2021 09:58:48 +0000 (11:58 +0200)]
drm/amdgpu: fix shadow bo skip condition
Create shadow BOs only for no-compute VM context and only for dGPU.
The existing if-condition would create shadow bo for compute context
on dGPU which not what we wanted.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Darren Powell [Wed, 26 May 2021 21:31:16 +0000 (17:31 -0400)]
amdgpu/pm: modify and add smu_get_power_limit to Powerplay API
modify args of smu_get_power_limit to match Powerplay API .get_power_limit
add smu_get_power_limit to Powerplay API swsmu_pm_funcs
remove special handling of smu in amdgpu_hwmon_show_power_cap*
Darren Powell [Sat, 22 May 2021 04:13:53 +0000 (00:13 -0400)]
amdgpu/pm: modify Powerplay API get_power_limit to use new pp_power enums
updated {amd_pm_funcs}->get_power_limit() signature
rewrote pp_get_power_limit to use new enums
pp_get_power_limit now returns -EOPNOTSUPP for unknown power limit
update calls to {amd_pm_funcs}->get_power_limit()
* Test Notes
* testing hardware was NAVI10 (tests SMU path)
** needs testing on VANGOGH
** needs testing on SMU < 11
** ie, one of
TOPAZ, FIJI, TONGA, POLARIS10, POLARIS11, POLARIS12, VEGAM, CARRIZO,
STONEY, VEGA10, VEGA12,VEGA20, RAVEN, BONAIRE, HAWAII
Darren Powell [Sat, 22 May 2021 02:37:24 +0000 (22:37 -0400)]
amdgpu/pm: clean up smu_get_power_limit function signature
add two new powerplay enums (limit_level, type)
add enums to smu_get_power_limit signature
remove input bitfield stuffing of output variable limit
update calls to smu_get_power_limit
Fix checkpatch.pl --strict -f drivers/gpu/drm/bridge/ti-sn65dsi83.c
CHECKs, no functional change. This is the same modification done
to V7 of the original patch.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Douglas Anderson <dianders@chromium.org> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Loic Poulain <loic.poulain@linaro.org> Cc: Marek Vasut <marex@denx.de> Cc: Philippe Schenker <philippe.schenker@toradex.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Valentin Raevsky <valentin@compulab.co.il>
To: dri-devel@lists.freedesktop.org Reviewed-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210608095322.23644-1-marex@denx.de
Christian König [Tue, 1 Jun 2021 17:47:50 +0000 (19:47 +0200)]
drm/ttm: nuke VM_MIXEDMAP on BO mappings v3
We discussed if that is really the right approach for quite a while now, but
digging deeper into a bug report on arm turned out that this is actually
horrible broken right now.
The reason for this is that vmf_insert_mixed_prot() always tries to grab
a reference to the underlaying page on architectures without
ARCH_HAS_PTE_SPECIAL and as far as I can see also enabled GUP.
So nuke using VM_MIXEDMAP here and use VM_PFNMAP instead.
Also make sure to reject mappings without VM_SHARED.
v2: reject COW mappings, merge function with only caller
v3: adjust comment as suggested by Thomas
Marek Vasut [Mon, 7 Jun 2021 17:42:58 +0000 (19:42 +0200)]
drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge
and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS
bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on,
but easy to add.
The driver operates the chip via I2C bus. Currently the LVDS clock are
always derived from DSI clock lane, which is the usual mode of operation.
Support for clock from external oscillator is not implemented, but it is
easy to add if ever needed. Only RGB888 pixel format is implemented, the
LVDS666 is not supported, but could be added if needed.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Douglas Anderson <dianders@chromium.org> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Loic Poulain <loic.poulain@linaro.org> Cc: Philippe Schenker <philippe.schenker@toradex.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Valentin Raevsky <valentin@compulab.co.il>
To: dri-devel@lists.freedesktop.org Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210607174258.16300-2-marex@denx.de
Marek Vasut [Mon, 7 Jun 2021 17:42:57 +0000 (19:42 +0200)]
dt-bindings: drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 bindings
Add DT binding document for TI SN65DSI83 and SN65DSI84 DSI to LVDS bridge.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Douglas Anderson <dianders@chromium.org> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: devicetree@vger.kernel.org
To: dri-devel@lists.freedesktop.org Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210607174258.16300-1-marex@denx.de
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Sat, 5 Jun 2021 14:43:00 +0000 (10:43 -0400)]
drm/amdgpu: Fix warning of Function parameter or member not described
Add the parameter table_freed description on function description.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wan Jiabing [Sat, 5 Jun 2021 02:54:06 +0000 (10:54 +0800)]
drm/amdkfd: remove duplicate include of kfd_svm.h
kfd_svm.h is included duplicately in commit 42de677f79999
("drm/amdkfd: register svm range").
After checking possible related header files,
remove the former one to make the code format more reasonable.
Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Sat, 5 Jun 2021 14:46:10 +0000 (16:46 +0200)]
drm/amdgpu: fix VM handling for GART allocations
For GTT allocations with a GART address the res contains the VMID0
addresses and can't be used for VM handling.
So ignore the res when the pages array is given or we fill the page
tables with nonsense.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peng Ju Zhou [Mon, 7 Jun 2021 05:40:56 +0000 (13:40 +0800)]
drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10
The NV12 and VEGA10 share the same interface W/RREG32_SOC15*,
the callback functions in these macros may not be defined,
so NULL pointer must be checked but not in
macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 3 Jun 2021 08:10:04 +0000 (16:10 +0800)]
drm/amdkfd: add sdma poison consumption handling
Follow the same apporach as GFX to handle SDMA
poison consumption. Send SIGBUS to application
when receives SDMA_ECC interrupt and issue gpu
reset either mode 2 or mode 1 to get the engine
back
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Fri, 4 Jun 2021 20:22:58 +0000 (16:22 -0400)]
drm/amdkfd: pages_addr offset must be 0 for system range
prange->offset is for VRAM range mm_nodes, if multiple ranges share same
mm_nodes, migrate range back to VRAM will reuse the VRAM at offset of
the same mm_nodes. For system memory pages_addr array, the offset is
always 0, otherwise, update GPU mapping will use incorrect system memory
page, and cause system memory corruption.
Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled
When PSR is enabled it handles DP_SDP_VSC, changing revision and all
the other fields as necessary.
It can also enabled and disable this SDP as needed without a full
modeset.
So here masking DP_SDP_VSC bit when previous and future state PSR
enabled, it will still be checked when comparing the asked state
to what was programmed to hardware.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514232247.144542-2-jose.souza@intel.com
Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware
configuration read out") is not allowing fastsets to happen when PSR
states changes but PSR is a feature that can be enabled and disabled
during fastsets.
So here moving the PSR pipe conf checks to a block that is only
executed when checking if HW state matches with requested state, not
during the phase where it checks if fastset is possible or not.
There still a state mismatch not allowing fastsets between states
turning off or on PSR because of crtc_state->infoframes.enable
BIT(DP_SDP_VSC) but at least for now it will allow a fastset between
PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not
work with PSR2, but the remaning issue will be fixed in a future patch.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210514232247.144542-1-jose.souza@intel.com
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