Chris Wilson [Mon, 28 Oct 2019 12:41:25 +0000 (12:41 +0000)]
drm/i915/execlists: Simply walk back along request timeline on reset
The request's timeline will only contain requests from this context, in
order of execution. Therefore, we can simply look back along this
timeline to find the currently executing request.
If we do find that the current context has completed its last request,
that does not imply that all requests are completed in the context, so
only advance the ring->head up to the end of the known completions!
Chris Wilson [Sun, 27 Oct 2019 22:58:07 +0000 (22:58 +0000)]
drm/i915/selftests: Use a random engine for GEM coherency tests
Select a random user accessible engine for checking coherency results.
While we should check all engines, we use a random selection so that
over repeated runs we cover all.
Chris Wilson [Sun, 27 Oct 2019 15:43:14 +0000 (15:43 +0000)]
drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
We would like some freedom to break the user API/ABI for future HW but
yet still expose the driver for upstream development on that HW.
Currently, we have the i915.force_probe module parameter to avoid binding
to HW while the driver is under development, but that is still a little
too soft with respect to the stringent no-regression rules if we also
plan to be redesigning the uAPI to go along with the new HW.
To allow the uAPI to be changed during development, only expose that API
and in development HW under STAGING (and BROKEN). Hopefully, making it
explicit that such interfaces to that HW are under development and not
to be blindly enabled by distributions.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Dave Airlie <airlied@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191027154314.11139-1-chris@chris-wilson.co.uk
Andi Shyti [Thu, 24 Oct 2019 21:16:41 +0000 (22:16 +0100)]
drm/i915: Extract GT render power state management
i915_irq.c is large. One reason for this is that has a large chunk of
the GT render power management stashed away in it. Extract that logic
out of i915_irq.c and intel_pm.c and put it under one roof.
Chris Wilson [Sat, 26 Oct 2019 08:22:20 +0000 (09:22 +0100)]
drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image
The location of RING_MI_MODE (used to stop the ring across resets) moved
for Tigerlake. Fixup the new location and include a selftest to verify
the location in the default context image.
Avoid angering clang and smatch by using a constant value in a '&&' test,
by forcing that constant value into a boolean.
E.g.,
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:159:13: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand]
if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) {
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Nathan Chancellor <natechancellor@gmail.com> Cc: Nick Desaulniers <ndesaulniers@google.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191025135943.12524-1-chris@chris-wilson.co.uk
Chris Wilson [Fri, 25 Oct 2019 16:54:42 +0000 (17:54 +0100)]
drm/i915/pmu: Initialise the spinlock before registering
As the GT may be running in parallel with the module initialisation
code, we may enter i915_pmu_gt_parked() as we are executing
i915_pmu_register(). We have to init the spinlock before we mark
pmu.event_init so that it is available for use by i915_pmu_gt_parked()
(which may run as soon as event_init is set).
Matthew Auld [Fri, 25 Oct 2019 17:25:11 +0000 (18:25 +0100)]
drm/i915/selftests/blt: add some kthreads into the mix
We can be more aggressive in our testing by launching a number of
kthreads, where each is submitting its own copy or fill batches on a set
of random sized objects. Also since the underlying fill and copy batches
can be pre-empted mid-batch(for particularly large objects), throw in a
random mixture of ctx priorities per thread to make pre-emption a
possibility.
Matthew Auld [Fri, 25 Oct 2019 15:37:28 +0000 (16:37 +0100)]
drm/i915/selftests: add sanity selftest for huge-GTT-pages
Now that for all the relevant backends we do randomised testing, we need
to make sure we still sanity check the obvious cases that might blow up,
such that introducing a temporary regression is less likely. Also
rather than do this for every backend, just limit to our two memory
types: system and local.
Matthew Auld [Fri, 25 Oct 2019 15:37:27 +0000 (16:37 +0100)]
drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.
Abdiel Janulgue [Fri, 25 Oct 2019 15:37:24 +0000 (16:37 +0100)]
drm/i915/lmem: support kernel mapping
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Steve Hampson <steven.t.hampson@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-3-chris@chris-wilson.co.uk
Matthew Auld [Fri, 25 Oct 2019 15:37:22 +0000 (16:37 +0100)]
drm/i915: support creating LMEM objects
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Lucas De Marchi [Thu, 24 Oct 2019 19:51:22 +0000 (12:51 -0700)]
drm/i915: split gen11_irq_handler to make it shareable
Split gen11_irq_handler() to receive as parameter the function
pointers. This allows to share the interrupt handler even if the enable/disable
functions are different.
Make sure it's always inlined to avoid the extra indirect call on the
hot path. Checking with gcc 9 this produce the exact same code as of
now:
$ size drivers/gpu/drm/i915/i915_irq*.o
text data bss dec hex filename
47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq.o
47511 560 0 48071 bbc7 drivers/gpu/drm/i915/i915_irq_new.o
Lucas De Marchi [Thu, 24 Oct 2019 19:51:21 +0000 (12:51 -0700)]
drm/i915: do not set MOCS control values on dgfx
On dgfx there's no LLC and eDRAM control table. Since now this
also means the device has global MOCS, just return early on the
initialization function.
L3 settings still apply and still need to be tweaked.
TGL introduced a feature in which we map the main surface to the
auxiliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.
Ville Syrjälä [Tue, 22 Oct 2019 18:56:43 +0000 (21:56 +0300)]
drm/i915: Fix PCH reference clock for FDI on HSW/BDW
The change to skip the PCH reference initialization during fastboot
did end up breaking FDI. To fix that let's try to do the PCH reference
init whenever we're disabling a DPLL that was using said reference
previously.
Cc: stable@vger.kernel.org Tested-by: Andrija <akijo97@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112084 Fixes: b16c7ed95caf ("drm/i915: Do not touch the PCH SSC reference if a PLL is using it") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191022185643.1483-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
Chris Wilson [Wed, 16 Oct 2019 22:57:30 +0000 (23:57 +0100)]
drm/i915/selftests: Force ordering of context switches
The parallel switch test has an underlying assumption that its requests
are executed in order of submission, which is only true if the backend
manages to keep up. Ensure the order of execution matches the submission
order by explicit dependencies and so when we wait on the last request,
we know we wait on completion of the entire queue.
Anna Karas [Thu, 26 Sep 2019 12:35:59 +0000 (15:35 +0300)]
drm/i915/tgl: Fix doc not corresponding to code
Replace PLLs names used in documentation to that used in the code.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Fixes: 68ff39c3f8c0 ("drm/i915/tgl: Add new pll ids") Signed-off-by: Anna Karas <anna.karas@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190926123559.15717-1-anna.karas@intel.com
Anna Karas [Tue, 22 Oct 2019 10:09:06 +0000 (13:09 +0300)]
doc: Update header files names
Update header files containing i915_perf_stream, i915_perf_stream_ops
and i915_oa_ops definitions since they have been moved from i915_drv.h
to i915_perf_types.h.
Cc: Robert Bragg <robert@sixbynine.org> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Anna Karas <anna.karas@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191022100906.16597-1-anna.karas@intel.com
Chris Wilson [Fri, 25 Oct 2019 09:27:49 +0000 (10:27 +0100)]
drm/i915/selftests: Tweak the default subtest runtime
BAT is growing a little fat and CI is under pressure and needs to trim
off some redundant runtime. An easy option is to reduce the selftest
runtimes, so try halving our default subtest timeout. While this reduces
the number of iterations used, for the majority of tests that are
passing, repeat runs (with different CI_DRM) will make up the
difference -- a negative consequence though is that we may reduce the
frequency of sporadic failures. Hopefully, we have no tests that were
crucially dependent on the previous 1s timeout...
drm/i915/display/psr: Print in debugfs if PSR is not enabled because of sink
Right now if sink reported any PSR error or if it fails to
acknowledge the PSR wakeup it sets a flag and do not attempt to
enable PSR anymore. That is the safest approach to avoid repetitive
glitches and allowed us to have PSR enabled by default.
But from time to time even good PSR panels have a PSR error, causing
tests to fail. And for now we are not yet to the point were we could
try to recover from PSR errors, so lets add this information to the
debugfs so IGT can check if PSR is disabled because of sink errors or
not and eliminate this noise from CI runs.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ap Kamal <kamal.ap@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191023214932.94679-1-jose.souza@intel.com
Matt Roper [Tue, 8 Oct 2019 21:17:16 +0000 (14:17 -0700)]
drm/i915: Catch GTT fault errors for gen11+ planes
Gen11+ has more hardware planes than gen9 so we need to test additional
pipe interrupt register bits to recognize any GTT faults that happen on
these extra planes.
As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.
Mika Kuoppala [Thu, 24 Oct 2019 11:03:31 +0000 (14:03 +0300)]
drm/i915: Remove nonpriv flags when srm/lrm
On testing the whitelists, using any of the nonpriv
flags when trying to access the register offset will lead
to failure.
Define address mask to get the mmio offset in order
to guard against any current and future flag usage.
v2: apply also on scrub_whitelisted_registers (Lionel)
Cc: Tapani Pälli <tapani.palli@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191024110331.8935-1-mika.kuoppala@linux.intel.com
Ville Syrjälä [Tue, 15 Oct 2019 19:30:31 +0000 (22:30 +0300)]
drm/i915: Add support for half float framebuffers for ivb+ sprites
ivb+ supports fp16 pixel formats on the sprite planes planes. Expose
that capability.
On ivb/hsw fp16 scanout is slightly busted. The output from the plane
will have 1/4 the expected value. For the sprite plane we can fix that
up with the plane gamma unit. This was fixed on bdw.
v2: Rebase on top of icl fp16
Split the ivb+ sprite birs into a separate patch
v3: Move ivb_need_sprite_gamma() check one level up so that
we don't waste time programming garbage into he gamma registers
Ville Syrjälä [Tue, 15 Oct 2019 19:30:30 +0000 (22:30 +0300)]
drm/i915: Add support for half float framebuffers for gen4+ primary planes
gen4+ supports fp16 pixel formats on the primary planes. Add the
relevant code.
On ivb fp16 scanout is slightly busted. The output from the plane will
have 1/4 the expected value. For the primary plane we would have to
use the pipe gamma or pipe csc to correct that which would affect all
the other planes as well, hence we simply choose not to expose fp16
on the ivb primary plane. On hsw the primary plane got fixed.
On gmch platforms I observed that the plane width must be below 2k
pixels with fp16 or else we get a corrupted image. This limitation
does not seem to be documented in bspec. I verified the exact limit
using the chv pipe B primary plane since it has windowing capability.
The stride limits are unaffected by fp16.
v2: Rebase on top of icl fp16
Split thea gen4+ primary plane bits into a separate patch
Deal with HAS_GMCH()
Ville Syrjälä [Tue, 15 Oct 2019 19:30:29 +0000 (22:30 +0300)]
drm/i915: Add support for half float framebuffers for skl+
skl+ supports fp16 pixel formats on all universal planes. Add the
necessary bits to expose that capability. The main different to
icl is that we can't scale fp16, so need to add the relevant
checks.
v2: Rebase on top of icl fp16
Split skl+ bits into a separate patch
Ville Syrjälä [Tue, 15 Oct 2019 19:30:28 +0000 (22:30 +0300)]
drm/i915: Simplify skl_max_scale()
Now that the planes declare their minimum cdclk requirements properly
we don't need to check the cdclk in skl_max_scale() anymore. Just check
against the maximum downscale ratio, and move the code next to it's
only caller.
The normal cdclk handling now takes care of making sure the
plane's pixel rate doesn't exceed the spec appointed percentage
of the cdclk frequency. Thus we can nuke
skl_check_pipe_max_pixel_rate().
Ville Syrjälä [Tue, 15 Oct 2019 19:30:26 +0000 (22:30 +0300)]
drm/i915: Allow planes to declare their minimum acceptable cdclk
Various pixel formats and plane scaling impose additional constraints
on the cdclk frequency. Provide a new plane->min_cdclk() hook that
will be used to compute the minimum acceptable cdclk frequency for
each plane.
Annoyingly on some platforms the numer of active planes affects
this calculation so we must also toss in more planes into the
state when the number of active planes changes.
The sequence of state computation must also be changed:
1. check_plane() (updates plane's visibility etc.)
2. figure out if more planes now require update min_cdclk
computaion
3. calculate the new min cdclk for each plane in the state
4. if the minimum of any plane now exceeds the current
logical cdclk we recompute the cdclk
4. during cdclk computation take the planes' min_cdclk into
accoutn
5. follow the normal cdclk programming to change the
cdclk frequency. This may now require a modeset (except
on bxt/glk in some cases), which either succeeds or
fails depending on whether userspace has given
us permission to perform a modeset or not.
v2: Fix plane id check in intel_crtc_add_planes_to_state()
Only print the debug message when cdclk needs bumping
Use dev_priv->cdclk... as the old state explicitly
check_digital_port_conflicts() is done needlessly late. Move it earlier.
This will be needed as later on we want to set any_ms=true a bit later
for non-modesets too and we can't call this guy without the
connection_mutex held.
Ville Syrjälä [Tue, 15 Oct 2019 19:30:24 +0000 (22:30 +0300)]
drm/i915: Rework global state locking
So far we've sort of protected the global state under dev_priv with
the connection_mutex. I wan to change that so that we can change the
cdclk even for pure plane updates. To that end let's formalize the
protection of the global state to follow what I started with the cdclk
code already (though not entirely properly) such that any crtc mutex
will suffice as a read lock, and all crtcs mutexes act as the write
lock.
We'll also pimp intel_atomic_state_clear() to clear the entire global
state, so that we don't accidentally leak stale information between
the locking retries.
As a slight optimization we'll only lock the crtc mutexes to protect
the global state, however if and when we actually have to poke the
hw (eg. if the actual cdclk changes) we must serialize commits
across all crtcs so that a parallel nonblocking commit can't get
ahead of the cdclk reprogamming. We do that by adding all crtcs to
the state.
TODO: the old global state examined during commit may still
be a problem since it always looks at the _latest_ swapped state
in dev_priv. Need to add proper old/new state for that too I think.
Ville Syrjälä [Tue, 15 Oct 2019 19:30:23 +0000 (22:30 +0300)]
drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll update
To make the logs a bit less confusing let's toss in some
debug prints to indicate whether the cdclk reprogramming
is going to happen with a single pipe active or whether we
need to turn all pipes off for the duration.
Chris Wilson [Wed, 23 Oct 2019 23:53:59 +0000 (00:53 +0100)]
drm/i915/selftests: Flush any i915_active callback work as well
Make trebly sure that all possible callbacks and their delayed brethren
are complete before asserting that the i915_active should be idle after
flushing all barriers.
We have the same CSB events being seen by process_csb() on two different
processors. One being issued by the reset in the test, the other by the
interrupt; this scenario is supposed to be prevented by flushing the
interrupt tasklet with tasklet_disable() before we enter the atomic
reset.
Zhenyu Wang [Wed, 23 Oct 2019 09:43:27 +0000 (17:43 +0800)]
drm/i915/gvt: fix dead locking in early workload shadow
As early workload scan and shadow happens in execlist mmio handler,
which has already taken vgpu_lock. So remove extra lock taking here.
Fixes: 952f89f098c7 ("drm/i915/gvt: Wean off struct_mutex") Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Wed, 23 Oct 2019 13:31:08 +0000 (14:31 +0100)]
drm/i915/gt: Replace hangcheck by heartbeats
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191023133108.21401-5-chris@chris-wilson.co.uk
Chris Wilson [Wed, 23 Oct 2019 13:31:07 +0000 (14:31 +0100)]
drm/i915/gem: Cancel contexts when hangchecking is disabled
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use endless batches and will disable
the hangcheck mechanism. We are looking at replacing hangcheck, in the
next patch, with a softer mechanism, that sends a pulse down the engine
to check if it is well. We can use the same preemptive pulse to flush an
active context off the GPU upon context close, preventing resources
being lost and unkillable requests remaining on the GPU after process
termination.
Testcase: igt/gem_ctx_exec/basic-nohangcheck Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191023133108.21401-4-chris@chris-wilson.co.uk
Chris Wilson [Wed, 23 Oct 2019 13:31:06 +0000 (14:31 +0100)]
drm/i915/execlists: Cancel banned contexts on schedule-out
On schedule-out (CS completion) of a banned context, scrub the context
image so that we do not replay the active payload. The intent is that we
skip banned payloads on request submission so that the timeline
advancement continues on in the background. However, if we are returning
to a preempted request, i915_request_skip() is ineffective and instead we
need to patch up the context image so that it continues from the start
of the next request.
v2: Fixup cancellation so that we only scrub the payload of the active
request and do not short-circuit the breadcrumbs (which might cause
other contexts to execute out of order).
v3: Grammar pass
Chris Wilson [Wed, 23 Oct 2019 13:31:05 +0000 (14:31 +0100)]
drm/i915/execlists: Force preemption
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of flagging unresponsive contexts more frequently (i.e. instead
of using an ~10s hangcheck, we now evict at ~100ms). The challenge of
lies in picking a timeout that can be reasonably serviced by HW for
typical workloads, balancing the existing clients against the needs for
responsiveness.
Note that coupled with timeslicing, this will lead to rapid GPU "hang"
detection with multiple active contexts vying for GPU time.
The forced preemption mechanism can be compiled out with
Chris Wilson [Wed, 23 Oct 2019 13:31:04 +0000 (14:31 +0100)]
drm/i915/gt: Try to more gracefully quiesce the system before resets
If we are doing a normal GPU reset triggered after detecting a long
period of stalled work, we can take our time and allow the engines to
quiesce. Since we've stopped submission to the engine, and if we wait
long enough an innocent context should complete, leaving the engine idle.
So by waiting a short amount of time, we should prevent clobbering other
users when resetting a stuck context.
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Suggested-by: Jon Bloomfield <jon.bloomfield@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191023133108.21401-1-chris@chris-wilson.co.uk
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191022163754.23870-2-robert.m.fosha@intel.com
Robert M. Fosha [Tue, 22 Oct 2019 16:37:52 +0000 (09:37 -0700)]
drm/i915/guc: Enable guc logging on guc log relay write
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
v2: Style changes and fix typos. Add guc_log_relay_stop()
function. (Daniele)
Cc: Matthew Brost <matthew.brost@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191022163754.23870-1-robert.m.fosha@intel.com
Imre Deak [Tue, 22 Oct 2019 09:51:55 +0000 (12:51 +0300)]
drm/i915: Add new CNL PCH ID seen on a CML platform
Atm we don't detect a PCH with PCI ID 0xA3C1 which showed up now on a CML
platform. We don't have the official assignment of the PCH PCI IDs, but
this looks like a CNP which was already used on CML platforms. Let's add
the new ID->PCH type mapping accordingly.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112051 Reported-and-tested-by: Cyrus <cyrus.lien@canonical.com> Cc: Cyrus <cyrus.lien@canonical.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191022095155.30991-1-imre.deak@intel.com
Jani Nikula [Tue, 22 Oct 2019 13:34:14 +0000 (16:34 +0300)]
drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config
DSC isn't DP specific, so remove the dp_ prefix from the crtc state
member name. Also moving the member under the dsc sub-struct gives us
enough context to allow shortening the name to just config. No
functional changes.
Jani Nikula [Tue, 22 Oct 2019 13:34:13 +0000 (16:34 +0300)]
drm/i915/dsc: rename crtc state dsc_params member to dsc
Reduce verbosity in code by renaming dsc_params member of crtc state to
simply dsc. There is enough context for this to be clear. No functional
changes.
Chris Wilson [Tue, 22 Oct 2019 22:33:16 +0000 (23:33 +0100)]
drm/i915/selftests: Release ctx->engine_mutex after iteration
A lock once taken must be released again.
Fixes: c31c9e82ee8a ("drm/i915/selftests: Teach switch_to_context() to use the context") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191022223316.12662-1-chris@chris-wilson.co.uk
Chris Wilson [Tue, 22 Oct 2019 11:21:11 +0000 (12:21 +0100)]
drm/i915/selftests: Synchronize checking active status with retirement
If retirement is running on another thread, we may inspect the status of
the i915_active before its retirement callback is complete. As we expect
it to be running synchronously, we can wait for any callback to complete
by acquiring the i915_active.mutex.
Chris Wilson [Tue, 22 Oct 2019 13:10:16 +0000 (14:10 +0100)]
drm/i915/selftests: Move uncore fw selftests to operate on intel_gt
Forcewake is the speciality of the GT, so it is natural to run the
intel_uncore_forcewake tests over the GT. So pass intel_gt as the
parameter to our selftests.
Chris Wilson [Tue, 22 Oct 2019 14:19:35 +0000 (15:19 +0100)]
drm/i915: Teach record_defaults to operate on the intel_gt
Again we wish to operate on the engines, which are owned by the
intel_gt. As such it is easier, and much more consistent, to pass the
intel_gt parameter.
Chris Wilson [Tue, 22 Oct 2019 12:28:45 +0000 (13:28 +0100)]
drm/i915: Drop assertion that ce->pin_mutex guards state updates
The actual conditions are that we know the GPU is not accessing the
context, and we hold a pin on the context image to allow CPU access. We
used a fake lock on ce->pin_mutex so that we could try and use lockdep
to assert that access is serialised, but the various different
hardirq/softirq contexts where we need to *fake* holding the pin_mutex
are causing more trouble.
Still it would be nice if we did have a way to reassure ourselves that
the direct update to the context image is serialised with GPU execution.
In the meantime, stop lockdep complaining about false irq inversions.
Chris Wilson [Tue, 22 Oct 2019 10:17:04 +0000 (11:17 +0100)]
drm/i915/selftests: Make the mman object busy everywhere
Loop over all engines, issuing a request for the object on each in order
to make sure we leave no stone unturned when creating an active ref. The
purpose is to make sure that we can reap a zombie object (one that is
only alive due to an active reference on the GPU) no matter where that
active reference emanates from.
Chris Wilson [Mon, 21 Oct 2019 18:32:35 +0000 (19:32 +0100)]
drm/i915: Lift i915_vma_parked() onto the gt
Currently even though i915_vma_parked() operates on a per-gt struct, it
is called from a global pm notify. This oddity was only because the long
term plan is to decouple the vma cache from the pm notification, but
right now the oddity stands out like a sore thumb!
Chris Wilson [Mon, 21 Oct 2019 17:43:39 +0000 (18:43 +0100)]
drm/i915/gt: Introduce barrier pulses along engines
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
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