Jonathan Zhou [Mon, 1 Feb 2021 18:13:50 +0000 (11:13 -0700)]
coresight: Add support for v8.4 SelfHosted tracing
v8.4 tracing extensions added support for trace filtering controlled
by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and
EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2
tracing if we are running the kernel at EL2.
Link: https://lore.kernel.org/r/20210110224850.1880240-29-suzuki.poulose@arm.com Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Will Deacon <will@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[ Move the trace filtering setup etm_init_arch_data() and clean ups] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-31-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
coresight: etm4x: Add support for sysreg only devices
Add support for devices with system instruction access only.
They don't have a memory mapped interface and thus are not
AMBA devices. System register access is not permitted to
TRCPDCR and thus skip access to them.
coresight: etm4x: Run arch feature detection on the CPU
As we are about to add support for system register based devices,
we don't get an AMBA pid. So, the detection code could check
the system registers running on the CPU to check for the architecture
specific features. Thus we move the arch feature detection to
run on the CPU. We cannot always read the PID from the HW, as the
PID could be overridden by DT for broken devices. So, use the
PID from AMBA layer if available.
CoreSight ETM with system register access may not have a
memory mapped i/o access. Refactor the ETM specific probing
into a common routine to allow reusing the code for such ETMs.
coresight: etm4x: Add necessary synchronization for sysreg access
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.
Expose the TRCDEVARCH register via the sysfs for component
detection. Given that the TRCIDR1 may not completely identify
the ETM component and instead need to use TRCDEVARCH, expose
this via sysfs for tools to use it for identification.
We are about to rely on TRCDEVARCH for detecting the ETM
and its architecture version, falling back to TRCIDR1 if
the former is not implemented (in older broken implementations).
Also, we use the architecture version information to
make some decisions. Streamline the architecture version
handling by adding helpers.
etm4_get_access_type() calculates the exception level bits
for use in address comparator registers. This is also used
by the TRCVICTLR register by shifting to the required position.
This patch cleans up the logic to make etm4_get_access_type()
calculate a generic mask which can be used by all users by
shifting to their field.
We rely on the ETM architecture version to decide whether
Secure EL2 is available on the CPU for excluding the level
for address comparators and viewinst main control register.
We must instead use the TRCDIDR3.EXLEVEL_S field to detect
the supported levels.
Define the fields of the DEVARCH register for identifying
a component as an ETMv4.x unit. Going forward, we use the
DEVARCH register for the component identification, rather
than the TRCIDR3.
coresight: etm4x: Hide sysfs attributes for unavailable registers
Some of the management registers in ETMv4.x are not accessible
via system register instructions. Thus we must hide the sysfs
files exposing them to the userspace, to prevent system crashes.
This patch adds an is_visible() routine to control the visibility
at runtime for the registers that may not be accessed.
ETM architecture defines the system instructions for accessing
via register accesses. Add basic support for accessing a given
register via system instructions.
We split the list of registers as :
1) Accessible only from memory mapped interface
2) Accessible from system register instructions.
All registers are accessible via the memory-mapped interface.
However, some registers are not accessible via the system
instructions. This list is then used to further filter out
the files we expose via sysfs.
As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to correlate.
coresight: etm4x: Make offset available for sysfs attributes
Some of the ETM management registers are not accessible via
system instructions. Thus we need to filter accesses to these
registers depending on the access mechanism for the ETM at runtime.
The driver can cope with this for normal operation, by regular
checks. But the driver also exposes them via sysfs, which now
needs to be removed.
So far, we have used the generic coresight sysfs helper macros
to export a given device register, defining a "show" operation
per register. This is not helpful to filter the files at runtime,
based on the access.
In order to do this dynamically, we need to filter the attributes
by offsets and hard coded "show" functions doesn't make this easy.
Thus, switch to extended attributes, storing the offset in the scratch
space. This allows us to implement filtering based on the offset and
also saves us some text size. This will be later used for determining
a given attribute must be "visible" via sysfs.
We don't want to replace them with the csdev_access_* to
avoid a function call for every register access for system
register access. This is a prepartory step to add system
register access later where the support is available.
coresight: tpiu: Prepare for using coresight device access abstraction
Prepare the TPIU driver to make use of the CoreSight device access
abstraction layer. The driver touches the device even before the
coresight device is registered. Thus we could be accessing the
devices without a csdev. As we are about to use the abstraction
layer for accessing the device, pass in the access directly
to avoid having to deal with the un-initialised csdev.
We are about to introduce support for sysreg access to ETMv4.4+
component. Since there are generic routines that access the
registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout)
and in order to preserve the logic of these operations at a
single place we introduce an abstraction layer for the accesses
to a given device.
coresight: etm4x: Skip accessing TRCPDCR in save/restore
When the ETM is affected by Qualcomm errata, modifying the
TRCPDCR could cause the system hang. Even though this is
taken care of during enable/disable ETM, the ETM state
save/restore could still access the TRCPDCR. Make sure
we skip the access during the save/restore.
Found by code inspection.
Link: https://lore.kernel.org/r/20210110224850.1880240-3-suzuki.poulose@arm.com Fixes: 02510a5aa78d ("coresight: etm4x: Add support to skip trace unit power up") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Cc: Tingwei Zhang <tingwei@codeaurora.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210201181351.1475223-5-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Merge tag 'misc-habanalabs-next-2021-01-27' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux into char-misc-next
Oded writes:
This tag contains habanalabs driver changes for v5.12:
- Add feature called "staged command submissions". In this feature,
the driver allows the user to submit multiple command submissions
that describe a single pass on the deep learning graph. The driver
tracks the completion of the entire pass by the last stage CS.
- Update code to support the latest firmware image
- Optimizations and improvements to MMU code:
- Support page size that is not power-of-2
- Make the locks scheme simpler
- mmap areas in device configuration space to userspace
- Security fixes:
- Make ETR non-secured
- Remove access to kernel memory through debug-fs interface
- Remove access through PCI bar to SyncManager register block
in Gaudi
- Many small bug fixes
* tag 'misc-habanalabs-next-2021-01-27' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux: (41 commits)
habanalabs: update to latest hl_boot_if.h spec from F/W
habanalabs/gaudi: unmask HBM interrupts after handling
habanalabs: update SyncManager interrupt handling
habanalabs: fix ETR security issue
habanalabs: staged submission support
habanalabs: modify device_idle interface
habanalabs: add CS completion and timeout properties
habanalabs: add new mem ioctl op for mapping hw blocks
habanalabs: fix MMU debugfs related nodes
habanalabs: add user available interrupt to hw_ip
habanalabs: always try to use the hint address
CREDITS: update email address and home address
habanalabs: update email address in sysfs/debugfs docs
habanalabs: add security violations dump to debugfs
habanalabs: ignore F/W BMC errors in case no BMC present
habanalabs/gaudi: print sync manager SEI interrupt info
habanalabs: Use 'dma_set_mask_and_coherent()'
habanalabs/gaudi: remove PCI access to SM block
habanalabs: add driver support for internal cb scheduling
habanalabs: increment ctx ref from within a cs allocation
...
Yang Li [Mon, 1 Feb 2021 07:30:40 +0000 (15:30 +0800)]
misc: rtsx: Remove unneeded return variable
This patch removes unneeded return variables, using only
'0' instead.
It fixes the following warning detected by coccinelle:
./drivers/misc/cardreader/rtsx_pcr.c:1808:5-8: Unneeded variable: "ret".
Return "0" on line 1833.
The size in header field for packet transferred over DMA
includes size of the extended header.
Include extended header in size check.
Add size and sanity checks on extended header.
Cc: <stable@vger.kernel.org> # v5.10+ Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20210129120752.850325-1-tomas.winkler@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Ohad Sharabi [Thu, 21 Jan 2021 20:25:52 +0000 (22:25 +0200)]
habanalabs: fix ETR security issue
ETR should always be non-secured as it is used by the users to record
profiling/trace data.
This patch fixes the configuration to match those requirements.
Ofir Bitton [Tue, 8 Dec 2020 11:47:05 +0000 (13:47 +0200)]
habanalabs: staged submission support
We introduce a new mechanism named Staged Submission.
This mechanism allows the user to send a whole CS in pieces.
Each CS will not require completion rather than the
last CS. Timeout timer will be triggered upon reception of the first
CS in group.
Ohad Sharabi [Sun, 17 Jan 2021 14:01:56 +0000 (16:01 +0200)]
habanalabs: modify device_idle interface
Currently this API uses single 64 bits mask for engines idle indication.
Recently, it was observed that more bits are needed for some ASICs.
This patch modifies the use of the idle mask and the idle_extensions
mask.
Ofir Bitton [Sun, 6 Dec 2020 15:18:02 +0000 (17:18 +0200)]
habanalabs: add CS completion and timeout properties
In order to support staged submission feature, we need to
distinguish on which command submission we want to receive
timeout and for which we want to receive completion.
farah kassabri [Tue, 12 Jan 2021 15:24:00 +0000 (17:24 +0200)]
habanalabs: fix MMU debugfs related nodes
In mmu debugfs node show un-scrambled physical addresses.
before read/write through data nodes, need to unscramble the
physical address before using it for pci transaction.
Ofir Bitton [Wed, 6 Jan 2021 13:40:37 +0000 (15:40 +0200)]
habanalabs: add user available interrupt to hw_ip
In order to support completions that arrive directly to the user,
the driver needs to supply the user with the first available msix
interrupt available.
farah kassabri [Mon, 11 Jan 2021 08:10:00 +0000 (10:10 +0200)]
habanalabs: always try to use the hint address
Currently hint address is ignored in case va block page size
is not power of 2. We need to support th user hint address also in this
case, but only if the hint address is aligned to page size.
Ofir Bitton [Tue, 5 Jan 2021 07:04:07 +0000 (09:04 +0200)]
habanalabs/gaudi: remove PCI access to SM block
Due to HW limitation we must remove all direct access to SM
registers, in order to do that we will access SM registers using
the HW QMANS.
When possible and no user context is present, we can directly access
the HW QMANS. Whenever there is an active user, driver will
prepare a pending command buffer list which will be sent upon
user submissions.
Ofir Bitton [Wed, 18 Nov 2020 13:46:57 +0000 (15:46 +0200)]
habanalabs: add driver support for internal cb scheduling
In order to support scnenarios in which driver needs access to
HW components but it cannot access them directly, we add support for
scheduling command buffers internally.
These command buffers will be transmitted upon next user command
submission context.
Ofir Bitton [Sun, 3 Jan 2021 12:13:06 +0000 (14:13 +0200)]
habanalabs: increment ctx ref from within a cs allocation
A CS must increment the relevant context reference count.
We want to increment the reference inside the CS allocation function
as opposed for today where we increment it outside.
This is logical since we want to avoid explicitly incrementing
the context every time we call the CS allocate function.
Ofir Bitton [Sun, 27 Dec 2020 15:09:09 +0000 (17:09 +0200)]
habanalabs: read device boot errors after cpucp is up
Boot cpu can report errors in various boot stages.
Current implementaion does not take into consideration errors
reported in late stages, hence we will check for errors at the most
late stage when fetching cpucp information.
Ofir Bitton [Thu, 31 Dec 2020 10:00:55 +0000 (12:00 +0200)]
habanalabs: report correct dram size in info ioctl
In case MMU is enabled, we must take MMU page size into
consideration when reporting dram size to the user.
This is because the MMU page size can be a value which is NOT
a power-of-2 value. As a result, the total DRAM size (which is always
a power-of-2 value) needed to be rounded-down.
Moti Haimovski [Wed, 18 Nov 2020 18:15:29 +0000 (20:15 +0200)]
habanalabs: support non power-of-2 DRAM phys page sizes
DRAM physical page sizes depend of the amount of HBMs available in
the device. this number is device-dependent and may also be subject
to binning when one or more of the DRAM controllers are found to
to be faulty. Such a configuration may lead to partitioning the DRAM
to non-power-of-2 pages.
To support this feature we also need to add infrastructure of address
scarmbling.
Ofir Bitton [Mon, 28 Dec 2020 16:28:08 +0000 (18:28 +0200)]
habanalabs: remove access to kernel memory using debugfs
Accessing kernel allocated memory through debugfs should not
be allowed as it introduces a security vulnerability.
We remove the option to read/write kernel memory for all asics.
Alon Mizrahi [Wed, 23 Dec 2020 15:53:17 +0000 (17:53 +0200)]
habanalabs: return dram virtual address in info ioctl
When working with DRAM MMU, we should supply the userspace with the
virtual start address of the DRAM instead of the physical one. This
is because the physical one has no meaning for the user as he only
knows the virtual address range.
Alon Mizrahi [Thu, 3 Dec 2020 15:32:19 +0000 (17:32 +0200)]
habanalabs: replace WARN/WARN_ON with dev_crit in driver
Often WARN is defined in data-centers as BUG and we would like to
avoid hanging the entire server on some internal error of the driver
(important as it might be).
Ohad Sharabi [Tue, 1 Dec 2020 12:06:27 +0000 (14:06 +0200)]
habanalabs/goya: move mmu_prepare to context init
Currently mmu_prepare is located at context switch.
Since we support a single context, no reason to reconfigure
the MMU registers every context switch.
Ioana Ciornei [Thu, 14 Jan 2021 17:07:52 +0000 (19:07 +0200)]
bus: fsl-mc: add autorescan sysfs
Add the autorescan sysfs in order to enable/disable the DPRC IRQs on
which automatic rescan of the bus is performed. This is important when
dynamic creation of objects is needed to happen in a timely manner because
object creation can be bundled together.
Ioana Ciornei [Thu, 14 Jan 2021 17:07:50 +0000 (19:07 +0200)]
bus: fsl-mc: add fsl-mc userspace support
Adding userspace support for the MC (Management Complex) means exporting
an ioctl capable device file representing the root resource container.
This new functionality in the fsl-mc bus driver intends to provide
userspace applications an interface to interact with the MC firmware.
Commands that are composed in userspace are sent to the MC firmware
through the FSL_MC_SEND_MC_COMMAND ioctl. By default the implicit MC
I/O portal is used for this operation, but if the implicit one is busy,
a dynamic portal is allocated and then freed upon execution.
The command received through the ioctl interface is checked against a
known whitelist of accepted MC commands. Commands that attempt a change
in hardware configuration will need CAP_NET_ADMIN, while commands used
in debugging do not need it.
Davidlohr Bueso [Fri, 15 Jan 2021 00:20:14 +0000 (16:20 -0800)]
platform/goldfish: Convert pipe tasklet to threaded irq
Tasklets have long been deprecated as being too heavy on the system
by running in irq context - and this is not a performance critical
path. If a higher priority process wants to run, it must wait for
the tasklet to finish before doing so. A more suitable equivalent
is to converted to threaded irq instead and deal with the signaled
pipes in task context.
ver_linux: Eliminate duplicate code in ldconfig processing logic
The code that acquires the version strings for libc and libcpp is
identical, as is the printversion call. The only difference being the
name of the library being printed.
Refactor the code by unifying the bits that are common to both libraries.
zhenwei pi [Sun, 10 Jan 2021 11:53:57 +0000 (19:53 +0800)]
misc: pvpanic: introduce device capability
According to pvpanic spec:
https://git.qemu.org/?p=qemu.git;a=blob_plain;f=docs/specs/pvpanic.txt
The guest should determine pvpanic capability by RDPT, so initialize
capability during device probing. There is no need to register panic
notifier callback function if no events supported.
Before sending event to host side, check capability firstly.
Suggested by Greg KH, use sysfs to expose capability to user space,
also add new sysfs attribute in document.
Andy Shevchenko [Fri, 22 Jan 2021 11:43:58 +0000 (13:43 +0200)]
misc: pti: Remove driver for deprecated platform
Intel Moorestown and Medfield are quite old Intel Atom based
32-bit platforms, which were in limited use in some Android phones,
tablets and consumer electronics more than eight years ago.
There are no bugs or problems ever reported outside from Intel
for breaking any of that platforms for years. It seems no real
users exists who run more or less fresh kernel on it. The commit 05f4434bc130 ("ASoC: Intel: remove mfld_machine") also in align
with this theory.
Due to above and to reduce a burden of supporting outdated drivers
we remove the support of outdated platforms completely.
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210122114358.39299-1-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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