* clk-unused:
clk: drop unused function __clk_get_flags
* clk-at91:
clk: at91: sama7g5: add clock support for sama7g5
clk: at91: clk-utmi: add utmi support for sama7g5
clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs
clk: at91: add macro for pll ids mask
clk: at91: clk-programmable: add mux_table option
clk: at91: clk-peripheral: add support for changeable parent rate
clk: at91: clk-master: add master clock support for SAMA7G5
clk: at91: clk-generated: add mux_table option
clk: at91: clk-generated: pass the id of changeable parent at registration
clk: at91: replace conditional operator with double logical not
clk: at91: sckc: register slow_rc with accuracy option
clk: at91: sam9x60: fix main rc oscillator frequency
clk: at91: sam9x60-pll: use frac when setting frequency
clk: at91: sam9x60-pll: check fcore against ranges
clk: at91: sam9x60-pll: use logical or for range check
clk: at91: clk-sam9x60-pll: fix mul mask
clk: at91: clk-generated: check best_rate against ranges
clk: at91: clk-generated: continue if __clk_determine_rate() returns error
clk: at91: fix possible dead lock in new drivers
Stephen Boyd [Mon, 3 Aug 2020 22:07:08 +0000 (15:07 -0700)]
Merge branches 'clk-fallthru', 'clk-ingenic', 'clk-tegra', 'clk-sirf' and 'clk-qoriq' into clk-next
- Add RTC related clks on Ingenic SoCs
- Support USB PHY clks on Ingenic SoCs
* clk-fallthru:
clk: davinci: Use fallthrough pseudo-keyword
clk: imx: Use fallthrough pseudo-keyword
* clk-ingenic:
clk: X1000: Add support for calculat REFCLK of USB PHY.
clk: JZ4780: Reformat the code to align it.
clk: JZ4780: Add functions for enable and disable USB PHY.
clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
dt-bindings: clock: Add tabs to align code.
dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.
Stephen Boyd [Mon, 3 Aug 2020 22:06:53 +0000 (15:06 -0700)]
Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
* clk-actions:
MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
clk: actions: Add Actions S500 SoC Reset Management Unit support
dt-bindings: reset: Add binding constants for Actions S500 RMU
clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
clk: actions: Fix h_clk for Actions S500 SoC
* clk-rockchip:
clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
clk: rockchip: use separate compatibles for rk3288w-cru
dt-bindings: clocks: add rk3288w variant compatible
clk: rockchip: Handle clock tree for rk3288w variant
clk: rockchip: convert rk3036 pll type to use internal lock status
clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout
clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout
* clk-iproc:
clk: iproc: round clock rate to the closest
* clk-intel:
clk: intel: Avoid unnecessary memset by improving code
clk: intel: Improve locking in the driver
clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()
* clk-debugfs:
clk: Add support for enabling/disabling clocks from debugfs
Stephen Boyd [Mon, 3 Aug 2020 22:06:45 +0000 (15:06 -0700)]
Merge branches 'clk-https', 'clk-renesas', 'clk-kconfig', 'clk-amlogic' and 'clk-imx' into clk-next
* clk-https:
Replace HTTP links with HTTPS ones: Common CLK framework
* clk-renesas:
clk: renesas: cpg-mssr: Add r8a774e1 support
dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
clk: renesas: Add r8a774e1 CPG Core Clock Definitions
dt-bindings: power: Add r8a774e1 SYSC power domain definitions
clk: renesas: rzg2: Mark RWDT clocks as critical
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
dt-bindings: clock: renesas: cpg: Convert to json-schema
* clk-kconfig:
clk: hsdk: Fix bad dependency on IOMEM
clk: Specify IOMEM dependency for HSDK pll driver
clk: Drop duplicate selection in Kconfig
clk: AST2600: Add mux for EMMC clock
clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
* clk-amlogic:
clk: meson: meson8b: add the vclk2_en gate clock
clk: meson: meson8b: add the vclk_en gate clock
clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
clk: meson: g12a: Add support for NNA CLK source clocks
dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
Stephen Boyd [Mon, 3 Aug 2020 22:06:16 +0000 (15:06 -0700)]
Merge branches 'clk-socfpga', 'clk-doc', 'clk-qcom', 'clk-vc5' and 'clk-bcm' into clk-next
- Enable CPU clks on Qualcomm IPQ6018 SoCs
- Enable CPU clks on Qualcomm MSM8996 SoCs
- GPU clk support for Qualcomm SM8150 and SM8250 SoCs
- Audio clks on Qualcomm SC7180 SoCs
- Make defines for bcm63xx-gate clks to use in DT
- Support gate clks on BCM6318 SoCs
- Add HDMI clks for BCM2711 SoCs
- Support BCM2711 SoC firmware clks
* clk-socfpga:
clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
* clk-doc:
clk: Clean up kernel-doc errors
clk: <linux/clk-provider.h>: drop a duplicated word
clk: add function documentation for clk_hw_round_rate()
* clk-qcom: (38 commits)
dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
clk: qcom: gcc-sdm660: Add missing modem reset
clk: qcom: lpass: Add support for LPASS clock controller for SC7180
clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
clk: qcom: gdsc: Add support to enable retention of GSDCR
clk: qcom: Export gdsc_gx_do_nothing_enable() to modules
clk: qcom: Add graphics clock controller driver for SM8250
clk: qcom: Add graphics clock controller driver for SM8150
clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
clk: qcom: gcc: remove unnecessary vco_table from SM8150
clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
clk: qcom: gcc: fix sm8150 GPU and NPU clocks
dt-bindings: clock: Fix qcom,msm8996-apcc yaml syntax
...
* clk-vc5:
clk: vc5: use a dedicated struct to describe the output drivers
dt-bindings: clk: versaclock5: convert to yaml
MAINTAINERS: take over IDT VersaClock 5 clock driver
dt-bindings: clk: versaclock5: fix 'idt' prefix typos
clk: vc5: Add memory check to prevent oops
clk: vc5: fix use of memory after it has been kfree'd
clk: vc5: Enable addition output configurations of the Versaclock
dt: Add additional option bindings for IDT VersaClock
clk: vc5: Allow Versaclock driver to support multiple instances
* clk-bcm: (44 commits)
clk: bcm2835: Do not use prediv with bcm2711's PLLs
dt-bindings: arm: bcm: Add a select to the RPI Firmware binding
clk: bcm: dvp: Add missing module informations
clk: bcm: rpi: Remove the quirks for the CPU clock
clk: bcm2835: Don't cache the PLLB rate
clk: bcm2835: Allow custom CCF flags for the PLLs
Revert "clk: bcm2835: remove pllb"
clk: bcm: rpi: Give firmware clocks a name
clk: bcm: rpi: Discover the firmware clocks
clk: bcm: rpi: Add an enum for the firmware clocks
clk: bcm: rpi: Add DT provider for the clocks
clk: bcm: rpi: Make the PLLB registration function return a clk_hw
clk: bcm: rpi: Split pllb clock hooks
clk: bcm: rpi: Rename is_prepared function
clk: bcm: rpi: Pass the clocks data to the firmware function
clk: bcm: rpi: Add clock id to data
clk: bcm: rpi: Create a data structure for the clocks
clk: bcm: rpi: Use CCF boundaries instead of rolling our own
clk: bcm: rpi: Make sure the clkdev lookup is removed
clk: bcm: rpi: Switch to clk_hw_register_clkdev
...
clk: bcm2835: Do not use prediv with bcm2711's PLLs
Contrary to previous SoCs, bcm2711 doesn't have a prescaler in the PLL
feedback loop. Bypass it by zeroing fb_prediv_mask when running on
bcm2711.
Note that, since the prediv configuration bits were re-purposed, this
was triggering miscalculations on all clocks hanging from the VPU clock,
notably the aux UART, making its output unintelligible.
Julia Lawall [Sat, 1 Aug 2020 08:53:42 +0000 (10:53 +0200)]
clk: drop unused function __clk_get_flags
The function __clk_get_flags has not been used since the April 2019
commit a348f05361c9 ("ARM: omap2+: hwmod: drop CLK_IS_BASIC
flag usage"). Other uses were removed in June 2015, eg by
commit 98d8a60eccee ("clk: Convert __clk_get_flags() to
clk_hw_get_flags()"), which shows how clk_hw_get_flags can easily
be used instead.
Douglas Anderson [Fri, 31 Jul 2020 20:30:10 +0000 (13:30 -0700)]
dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
The YAML schemas that landed forgot one clock: "bi_tcxo". Presumably
the bindings were developed against the v4 version of the driver and
when the ".name" was removed in v5 of the driver things broke.
While touching this, add the needed includes in each example. I
believe both examples are supposed to be independent of each other.
The kernel test robot points out two harmless warnings in the
mmp clk drivers:
drivers/clk/mmp/clk-pxa168.c:68:13: warning: no previous prototype for 'pxa168_clk_init' [-Wmissing-prototypes]
drivers/clk/mmp/clk-pxa910.c:66:13: warning: no previous prototype for 'pxa910_clk_init' [-Wmissing-prototypes]
Xu Wang [Mon, 13 Jul 2020 03:21:43 +0000 (03:21 +0000)]
clk: clk-atlas6: fix return value check in atlas6_clk_init()
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/r/20200713032143.21362-1-vulab@iscas.ac.cn Acked-by: Barry Song <baohua@kernel.org> Fixes: 7bf21bc81f28 ("clk: sirf: re-arch to make the codes support both prima2 and atlas6") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Power Management Controller (PMC) can override the PLLM clock settings,
including the enable-state. Although PMC could only act as a second level
gate, meaning that PLLM needs to be enabled by the Clock and Reset
Controller (CaR) anyways if we want it to be enabled. Hence, when PLLM is
overridden by PMC, it needs to be enabled by CaR and ungated by PMC in
order to be functional. Please note that this patch doesn't fix any known
problem, and thus, it's merely a minor improvement.
clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
The RTC unit in the Ingenic SoCs has two clock sources, one
is from an external 32.768kHz clock, and the other is from an
external 24MHz/48MHz main clock that is divided by 512. The
choice of these two clocks is controlled by the ERCS bit in
the OPCR register. The RNG unit will also use this clock.
The "JZ4780_CLK_LCD0PIXCLK" and the "JZ4780_CLK_LCD1PIXCLK"
in the "jz4780.h" and the new added "JZ4780_CLK_EXCLK_DIV512"
in the previous patch is too long, add tabs to other lines
to align them.
Taniya Das [Fri, 24 Jul 2020 16:07:56 +0000 (21:37 +0530)]
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Taniya Das [Fri, 24 Jul 2020 16:07:55 +0000 (21:37 +0530)]
clk: qcom: gdsc: Add support to enable retention of GSDCR
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.
clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs
Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
For these, split the PLL clock in two: fractional clock and
divider clock. In case PLLs supports multiple outputs (since these
outputs are dividers (with different settings) sharing the same
fractional part), it will register one fractional clock and multiple
divider clocks (dividers sharing the fractional clock).
clk: at91: clk-peripheral: add support for changeable parent rate
Some peripheral clocks on SAMA7G5 supports requesting parent to change
its rate (image related clocks: csi, csi2dc, isc). Add support
so that if registered with this option the clock rate to be
requested from parent.
clk: at91: clk-master: add master clock support for SAMA7G5
Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.
clk: at91: clk-generated: pass the id of changeable parent at registration
Pass the ID of changeable parent at registration. This will allow
the scalability of this clock driver with regards to the changeable
parent ID for versions of this IP where changeable parent is not the
last one in the parents list (e.g. SAMA7G5). With this the clock flags
are set to zero in case we have no changeable parent. Also in
clk_generated_best_diff() the *best_diff variable is check against
tmp_diff variable using ">=" operator instead of ">" so that in case
the requested frequency could be obtained using fix parents + gck
dividers but the clock also supports changeable parent to be able
to force the usage of the changeable parent.
clk: at91: sckc: register slow_rc with accuracy option
Chapter 57.7.5 of SAM9X60 datasheet specifies that the maximum drift of
this oscillator is +- 3KHz. Use that value and the formula at [1]
or the calculator at [2] to compute the PPB value.
clk: at91: sam9x60-pll: use frac when setting frequency
In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).
clk: at91: sam9x60-pll: check fcore against ranges
According to datasheet the range of 600-1200MHz is for the
frequency generated by the fractional part of the PLL (namely
Fcorepllck according to datasheet). With this in mind the output
range of the PLL itself (fractional + div), taking into account
that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz.
clk: at91: sam9x60-pll: use logical or for range check
Use logical or for range check. In case bestrate is not in
characteristics->output[0].min..characteristics->output[0].max
range we should return -ERANGE.
Ahmad Fatoum [Fri, 3 Jul 2020 07:32:35 +0000 (09:32 +0200)]
clk: at91: fix possible dead lock in new drivers
syscon_node_to_regmap() will make the created regmap get and enable the
first clock it can parse from the device tree. This clock is not needed to
access the registers and should not be enabled at that time.
Use device_node_to_regmap to resolve this as it looks up the regmap in
the same list but doesn't care about the clocks. This issue is detected
by lockdep when booting the sama5d3 with a device tree containing the
new clk bindings.
This fix already happened in 6956eb33abb5 ("clk: at91: fix possible
deadlock") for the drivers that had been migrated to the new clk binding
back then. This does the same for the new drivers as well.
Mike Tipton [Tue, 30 Jun 2020 00:30:24 +0000 (17:30 -0700)]
clk: Add support for enabling/disabling clocks from debugfs
For test and debug purposes, it's simple enough to enable or disable
clocks from shell. Add a new debugfs file 'clk_prepare_enable' that
calls clk_prepare_enable() when writing "1" and clk_disable_unprepare()
when writing "0".
This can have security implications, so only support it when the code
has been modified to #define CLOCK_ALLOW_WRITE_DEBUGFS.
Lori Hikichi [Fri, 12 Jun 2020 22:52:12 +0000 (15:52 -0700)]
clk: iproc: round clock rate to the closest
Change from 'DIV_ROUND_UP' to 'DIV_ROUND_CLOSEST' when calculating the
clock divisor in the iProc ASIU clock driver to allow to get to the
closest clock rate.
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Signed-off-by: Lori Hikichi <lhikichi@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Link: https://lore.kernel.org/r/20200612225212.124301-1-ray.jui@broadcom.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8250 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-9-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8150 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-8-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Marek [Thu, 9 Jul 2020 13:52:37 +0000 (09:52 -0400)]
dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 gpucc bindings.
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-7-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.
Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Marek [Thu, 9 Jul 2020 13:52:32 +0000 (09:52 -0400)]
clk: qcom: gcc: fix sm8150 GPU and NPU clocks
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it
should be a 500us delay and not skip, however this matches what was done
for other clocks that had 500us delay in downstream.
Fixes: f73a4230d5bb ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-2-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: vc5: use a dedicated struct to describe the output drivers
Reusing the generic struct vc5_hw_data for all blocks is handy. However it
implies we allocate space the div_int and div_frc fields even for the
output drivers where they are unused, and the clk_output_cfg0 and
clk_output_cfg0_mask fields for all components even though they are used
only for the output drivers.
Use a dedicated struct for the output drivers so that each block uses
exactly the fields it needs, not more.
Convert to yaml the VersaClock bindings document. The mapping between
clock specifier and physical pins cannot be described formally in yaml
schema, then keep it verbatim in the description field.
Maxime Ripard [Fri, 26 Jun 2020 11:54:33 +0000 (13:54 +0200)]
dt-bindings: arm: bcm: Add a select to the RPI Firmware binding
The RaspberryPi firmware binding uses two compatible, include simple-bus.
The select statement generated by default will thus select any node that
has simple-bus, not all of them being the raspberrypi firmware node.
This results in warnings being wrongfully reported. Let's add a custom
select statement to fix that.
Fixes: d4c708c032df ("dt-bindings: arm: bcm: Convert BCM2835 firmware binding to YAML") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200626115433.125735-1-maxime@cerno.tech Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Thu, 23 Jul 2020 01:52:51 +0000 (18:52 -0700)]
Merge tag 'v5.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
Use poll_timeout functions for pll lock-waiting and move the rk3036 to use
the available lock-status in pll-registers instead of reading it from the
General Register Files. Handle the clock variants on the rk3288w, revert
the mmc sample shift change on rk3328 and make the mac_lbtest clock
critical on rk3188.
* tag 'v5.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
clk: rockchip: use separate compatibles for rk3288w-cru
dt-bindings: clocks: add rk3288w variant compatible
clk: rockchip: Handle clock tree for rk3288w variant
clk: rockchip: convert rk3036 pll type to use internal lock status
clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout
clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout
Adam Ford [Thu, 16 Jul 2020 12:26:20 +0000 (07:26 -0500)]
clk: vc5: Add memory check to prevent oops
When getting the names of the child nodes, kasprintf is used to
allocate memory which is used to create the string for the node
name. Unfortunately, there is no memory check to determine
if this allocation fails, it may cause an error when trying
to get child node name.
This patch will check if the memory allocation fails, and returns
and -ENOMEM error instead of blindly moving on.
Fixes: 260249f929e8 ("clk: vc5: Enable addition output configurations of the Versaclock") Suggested-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20200716122620.4538-1-aford173@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Colin Ian King [Thu, 25 Jun 2020 13:27:36 +0000 (14:27 +0100)]
clk: vc5: fix use of memory after it has been kfree'd
There are a several places where printing an error message of
init.name occurs after init.name has been kfree'd. Also the failure
message is duplicated each time in the code. Fix this by adding
a registration error failure path for these cases, moving the
duplicated error messages to one common point and kfree'ing init.name
only after it has been used.
Changes also shrink the object code size by 171 bytes (x86-64, gcc 9.3):
Before:
text data bss dec hex filename
21057 3960 64 25081 61f9 drivers/clk/clk-versaclock5.o
After:
text data bss dec hex filename
20886 3960 64 24910 614e drivers/clk/clk-versaclock5.o
Addresses-Coverity: ("Use after free") Fixes: f491276a5168 ("clk: vc5: Allow Versaclock driver to support multiple instances") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200625132736.88832-1-colin.king@canonical.com Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
[sboyd@kernel.org: Drop stray newline] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alex Bee [Wed, 22 Jul 2020 16:18:20 +0000 (18:18 +0200)]
clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
Since the loopbacktest clock is not exported and is not touched in the
driver, it has to be added to rk3188_critical_clocks to be protected from
being disabled and in order to get the emac working.
Stephen Boyd [Tue, 21 Jul 2020 07:58:07 +0000 (00:58 -0700)]
Merge tag 'clk-meson-v5.9-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- g12: add neural network accelerator clock sources
- meson8: remove critical flag for main PLL divider
- meson8: add video decoder clock gates
* tag 'clk-meson-v5.9-1' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: add the vclk2_en gate clock
clk: meson: meson8b: add the vclk_en gate clock
clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
clk: meson: g12a: Add support for NNA CLK source clocks
dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
Taniya Das [Wed, 15 Jul 2020 06:54:10 +0000 (12:24 +0530)]
clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
The display gpll0 branch clock inside GCC needs to always be enabled.
Otherwise the AHB clk (disp_cc_mdss_ahb_clk_src) for the display clk
controller (dispcc) will stop clocking while sourcing from gpll0 when
this branch inside GCC is turned off during unused clk disabling. We can
never turn this branch off because the AHB clk for the display subsystem
is needed to read/write any registers inside the display subsystem
including clk related ones. This makes this branch a really easy way to
turn off AHB access to the display subsystem and cause all sorts of
mayhem. Let's just make the clk ops keep the clk enabled forever and
ignore any attempts to disable this clk so that dispcc accesses keep
working.
Signed-off-by: Taniya Das <tdas@codeaurora.org> Reported-by: Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/1594796050-14511-1-git-send-email-tdas@codeaurora.org Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
[sboyd@kernel.org: Fill out commit text more] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Randy Dunlap [Sun, 19 Jul 2020 00:28:30 +0000 (17:28 -0700)]
clk: <linux/clk-provider.h>: drop a duplicated word
Drop the repeated word "not" in a comment.
Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20200719002830.20319-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
David Gow [Tue, 30 Jun 2020 04:32:14 +0000 (21:32 -0700)]
clk: Specify IOMEM dependency for HSDK pll driver
The HSDK pll driver uses the devm_ioremap_resource function, but does
not specify a dependency on IOMEM in Kconfig. This causes a build
failure on architectures without IOMEM, for example, UML (notably with
make allyesconfig).
Fix this by making CONFIG_CLK_HSDK depend on CONFIG_IOMEM.
Eddie James [Thu, 9 Jul 2020 19:57:05 +0000 (14:57 -0500)]
clk: AST2600: Add mux for EMMC clock
The EMMC clock can be derived from either the HPLL or the MPLL. Register
a clock mux so that the rate is calculated correctly based upon the
parent.
Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20200709195706.12741-2-eajames@linux.ibm.com Acked-by: Joel Stanley <joel@jms.id.au> Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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