Fabio Estevam [Fri, 4 Nov 2022 11:12:54 +0000 (08:12 -0300)]
wandboard: Pass mmc aliases
Originally, the mmc aliases node was present in imx6qdl-wandboard.dtsi.
After the sync with Linux in commit c2092e38fd66 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a regression in which the SD card cannot be found anymore:
Since commit the aliases node has been removed
U-Boot 2022.10-00999-gcca41ed3d63f-dirty (Nov 03 2022 - 22:07:38 -0300)
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
Core: 62 devices, 17 uclasses, devicetree: separate
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the SD card (esdhc3) was
mapped to mmc0.
Fixes: c2092e38fd66 ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 13:43:41 +0000 (08:43 -0500)]
configs: imx8mn_beacon: Re-align memory to standard imx8mn settings
The imx8mn_beacon board does not use the same memory map as the reference
design from NXP or other imx8mn boards. As such, memory is more limited
in SPL.
Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases
the amount of available meory for the SPL stack. Doing this allows
the board to no longer define CONFIG_MALLOC_F_ADDR.
Since SYS_LOAD_ADDR also does not align with other boards, move it too.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marcel Ziswiler [Mon, 7 Nov 2022 21:22:36 +0000 (22:22 +0100)]
imxrt1050: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.
Note: Nowadays, the intent is for them regular device trees to just be
synchronised from them Linux kernel device trees and any and all U-Boot
specific changes need to go into the -u-boot.dtsi device tree include
files which BTW get included automatically by the U-Boot build system.
The IMX8M based Venice boards all have device-tree fec nodes that
use proper dt with a phy-handle pointing to a phy with reg assigned
to the proper phy address.
There is no need to keep using the CONFIG_FEC_MXC_PHYADDR hack when
a proper dt is used - remove it.
This was previously done in commit c5169b4f156a
("configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR")
but got clobbered by commit 0d123e98b705
("Convert CONFIG_SYS_BARGSIZE to Kconfig")
Tim Harvey [Fri, 4 Nov 2022 15:43:06 +0000 (08:43 -0700)]
board: gateworks: venice: remove redundance adjustment of thermal trip points
commit 170edb8d4d59 ("imx8m: fixup thermal trips") moved updating the
thermal trip points to all IMX8M so we can remove it from our board
specific dt config.
Martyn Welch [Tue, 25 Oct 2022 09:55:01 +0000 (10:55 +0100)]
drivers: power: pmic: Enable use of rn5t567 PMIC in SPL
The support added later in this series tweaks the PMIC voltages in the
SPL. Enable support for the rn5t567 in SPL builds to allow this to be done
cleanly.
Adam Ford [Sat, 22 Oct 2022 14:28:24 +0000 (09:28 -0500)]
imx: imx8mm-beacon: Move Environment to eMMC partition 2
The downstream U-Boot distributed by Beacon stores the environment
in the eMMC and the end of partition 2. This allow the environment
to stay on the SOM regardless of the boot source.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 14:28:23 +0000 (09:28 -0500)]
imx: imx8mm-beacon: Enable USB booting via SDP
In order to boot over USB, the device tree needs to enable
a few extra nodes in SPL. Since the USB driver has the
ability to detect host/device, the dr_mode can be removed
from the device tree since it needs to act as a device when
booting and OTG is the default mode. Add USB boot support
to spl_board_boot_device and enable the corresponding config
options.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 14:28:22 +0000 (09:28 -0500)]
imx: imx8mm_beacon: Eliminate a few extras to free up SPL space
There are a few functions which are not essential for use in
SPL, but they take up enough space to make other preferred
features not fit. Remove the extras.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 13:43:44 +0000 (08:43 -0500)]
imx: imx8mn-beacon: Fix out of spec voltage
The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit before initializing LPDDR4
or it will be running out of spec.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Sat, 22 Oct 2022 13:43:42 +0000 (08:43 -0500)]
regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled
If the bd718x7 is required, but PMIC_CHILDREN is disabled, this
driver throws a compile error. Fix this by putting the function
to bind children into an if-statement checking for PMIC_CHILDREN.
Allowing PMIC_CHILDREN to be disabled in SPL saves some space and
still permits some read/write functions to access the PMIC in
early startup.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Estevam <festevam@gmail.com>
- The code intended to temporarily mask all interrupts in GPC_IMRx_CORE0.
While the old register values were saved, the actual masking was
missing.
- imx_udelay() expects the system counter to run at its base frequency,
but the system counter is switched to a lower frequency earlier in
psci_system_suspend(), leading to a much longer delay than intended.
Replace the call with an equivalent loop (linux-imx 5.15 does the same)
This fixes the SoC hanging forever when there was already a wakeup IRQ
pending while suspending.
Chris Packham [Sat, 5 Nov 2022 04:24:00 +0000 (17:24 +1300)]
arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Sat, 5 Nov 2022 04:23:59 +0000 (17:23 +1300)]
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Sat, 5 Nov 2022 04:23:57 +0000 (17:23 +1300)]
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Sat, 5 Nov 2022 04:23:56 +0000 (17:23 +1300)]
net: mvneta: Add support for AlleyCat5
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Sat, 5 Nov 2022 04:23:55 +0000 (17:23 +1300)]
arm: mvebu: Don't use CONFIG_TIMER on ARM64
The 64-bit mvebu SoCs don't have a suitable timer driver so add a !ARM64
condition to the select.
Fixes: 2325ebcdff ("arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms") Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 2 Nov 2022 17:51:28 +0000 (18:51 +0100)]
Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwb
File name with pattern u-boot-spl* is used on all places except in kwb
image for binary with SPL-only code. Combined binary with both SPL and
proper U-Boot in other places has file name pattern u-boot-with-spl*.
Make it consistent also for kwb image and rename u-boot-spl.kwb to
u-boot-with-spl.kwb as this image contains both SPL and proper U-Boot code.
Also update documentation about file name changes.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Hamish Martin [Thu, 20 Oct 2022 21:21:59 +0000 (10:21 +1300)]
arm: armada: dts: Add clock to armada-ap80x uart1
The uart1 node was missing the 'clock-frequency' property. This meant
the driver for this device would fail at probe.
The clock for uart1 is fed from the same source as uart0 and is a fixed
200MHz clock. This is confirmed via documentation for the CN9130 SoC
and from the equivalent code in Linux at:
<linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
where uart0 and uart1 share a common 'clocks' definition.
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Reviewed-by: Stefan Roese <sr@denx.de>
AllocatePages() can be called with Type=AllocateAddress. Such a call can
only succeed if *Memory points to the address of an unallocated page range.
A call with *Memory being an address that is not page aligned must not
succeed. The UEFI specification requires returning EFI_OUT_OF_RESOURCES
if the requested pages cannot be allocated.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
AKASHI Takahiro [Fri, 21 Oct 2022 03:01:57 +0000 (12:01 +0900)]
efi_loader: remove CONFIG_EFI_SETUP_EARLY
Since the commit 3da94f1971c7 ("efi_loader: disk: a helper function to
create efi_disk objects from udevice"), CONFIG_EFI_SETUP_EARLY option is
by default on and will never be turned off.
Jan Kiszka [Fri, 14 Oct 2022 16:10:06 +0000 (18:10 +0200)]
efi_loader: Let networking support depend on NETDEVICES
CONFIG_NET does not imply that there are actually network devices
available, only CONFIG_NETDEVICES does. Changing to this dependency
obsoletes the check in Kconfig because NETDEVICES means DM_ETH.
Fixes: 0efe1bcf5c2c ("efi_loader: Add network access support") Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Thu, 3 Nov 2022 18:25:44 +0000 (14:25 -0400)]
docs: Add a basic security document
Based loosely on the Linux kernel
Documentation/admin-guide/security-bugs.rst file, create a basic
security document for U-Boot. In sum, security issues should be
disclosed in public on the mailing list if at all possible as an initial
position.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Marek Vasut [Sun, 30 Oct 2022 22:38:35 +0000 (23:38 +0100)]
usb: Add 1ms delay after first Get Descriptor request
Logitech Unifying Receiver 046d:c52b bcdDevice 12.10 seems
sensitive about the first Get Descriptor request. If there
are any other requests in the same microframe, the device
reports bogus data, first of the descriptor parts is not
sent to the host. Wait over one microframe duration before
issuing subsequent requests to avoid probe failure with
this device, since it can be used to connect USB keyboards.
Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Janne Grunau <j@jannau.net>
Padmarao Begari [Thu, 27 Oct 2022 06:02:02 +0000 (11:32 +0530)]
riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip QSPI driver and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for
the HSS to use.
Padmarao Begari [Thu, 27 Oct 2022 06:01:59 +0000 (11:31 +0530)]
riscv: dts: Update memory configuration
In the v2022.10 Icicle reference design, the seg registers have been
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific context.
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
Stefan Roese [Fri, 28 Oct 2022 12:46:29 +0000 (14:46 +0200)]
mips: mtmips: spl/Kconfig: Set CONFIG_SPL_PAD_TO to 0x0 for ARCH_MTMIPS
It was noticed that while converting CONFIG_SPL_PAD_TO to Kconfig its
value for the MIPS MT762x/8x targets got not ported correctly. Its
default is not 0x10000 instead of 0x0. This patch fixes this issue.
Fixes: 4f2244201417 ("Convert CONFIG_SPL_PAD_TO et al to Kconfig") Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ruben Winters <Ruben.Winters@gooiland-elektro.nl> Cc: Weijie Gao <weijie.gao@mediatek.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Tom Rini <trini@konsulko.com>
Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
Remove code which depends on CONFIG_SYS_MHZ but where no board configs
actually use that code.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Baruch Siach [Sun, 23 Oct 2022 09:28:12 +0000 (12:28 +0300)]
cmd: eeprom: don't truncate target address at 32-bit
On 64-bit platforms where int is 32-bit wide, the eeprom command
parse_numeric_param() routine truncates the memory address parameter to
the lower 32-bit. Make parse_numeric_param() return long to allow
read/write of addresses beyond the lower 4GB.
Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Andre Przywara [Thu, 20 Oct 2022 22:10:25 +0000 (23:10 +0100)]
highbank: switch to use the Arm SP804 DM_TIMER driver
So far the Calxeda machines were using the CONFIG_SYS_TIMER_* macros to
simply hardcode the address of the counter register of the SP804 timer.
This method is deprecated and scheduled for removal.
Use the newly introduced SP804 DM_TIMER driver to provide timer
functionality on Highbank and Midway machines. The base address and base
frequency are taken from the devicetree.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 20 Oct 2022 22:10:24 +0000 (23:10 +0100)]
highbank: scan into hb_sregs DT subnodes
The DT used for Calxeda Highbank and Midway systems exposes a "system
registers" block, modeled as a DT subnode.
This includes several clocks, including the two fixed clocks for the
main oscillator and timer.
So far U-Boot was ignorant of this special construct (a "clocks" node
within the "hb-sregs" node), as it didn't need the PLL clocks in there.
But that also meant we lost the fixed clocks, which form the base for
the UART baudrate generator and also the SP804 timer.
To allow the generic PL011 and SP804 driver to read the clock rate,
add a simple bus driver, which triggers the DT node discovery inside this
special node. As we only care about the fixed clocks (we don't have
drivers for the PLLs anyway), just ignore the address translation (for
now).
The binding is described in bindings/arm/calxeda/hb-sregs.yaml, the DT
snippet in question looks like:
Andre Przywara [Thu, 20 Oct 2022 22:10:23 +0000 (23:10 +0100)]
timer: add SP804 UCLASS timer driver
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.
Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.
This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.
The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 Oct 2022 16:38:49 +0000 (17:38 +0100)]
arm: smh: Allow semihosting trap calls to be inlined
Currently our semihosting trap function is somewhat fragile: we rely
on the current compiler behaviour to assign the second inline assembly
argument to the next free register (r1/x1), which happens to be the
"addr" argument to the smh_trap() function (per the calling convention).
I guess this is also the reason for the noinline attribute.
Make it explicit what we want: the "addr" argument needs to go into r1,
so we add another register variable. This allows to drop the "noinline"
attribute, so now the compiler beautifully inlines just the trap
instruction directly into the calling function.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 Oct 2022 16:38:48 +0000 (17:38 +0100)]
arm: smh: Make semihosting trap calls more robust
Commit 5ab1739c3ff8("arm: smh: Fix uninitialized parameters with newer
GCCs") added a memory clobber to the semihosting inline assembly trap
calls, to avoid too eager GCC optimisation: when passing a pointer, newer
compilers couldn't be bothered to actually fill in the structure that it
pointed to, as this data would seemingly never be used (at least from the
compiler's point of view).
But instead of the memory clobber we need to tell the compiler that we are
passing an *array* instead of some generic pointer, this forces the
compiler to actually populate the data structure.
This involves some rather hideous cast, which is best hidden in a macro.
But regardless of that, we actually need the memory clobber, but for two
different reasons: explain them in comments.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 Oct 2022 16:38:47 +0000 (17:38 +0100)]
arm: smh: specify Thumb trap instruction
The ARM semihosting interface uses different trap instructions for
different architectures and instruction sets. So far we were using
AArch64 and ARMv7-M, and had an untested v7-A entry. The latter does
not work when building for Thumb, as can be verified by using
qemu_arm_defconfig, then enabling SEMIHOSTING and SYS_THUMB_BUILD:
==========
{standard input}:35: Error: invalid swi expression
{standard input}:35: Error: value of 1193046 too large for field of 2 bytes at 0
==========
Fix this by providing the recommended instruction[1] for Thumb, and
using the ARM instruction only when not building for Thumb. This also
removes some comment, as QEMU for ARM allows to now test this case.
Also use the opportunity to clean up the inline assembly, and just define
the actual trap instruction inside #ifdef's, to improve readability.
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:54 +0000 (13:50 +0200)]
cyclic: get rid of cyclic_init()
Currently, we must call cyclic_init() at some point before
cyclic_register() becomes possible. That turns out to be somewhat
awkward, especially with SPL, and has resulted in a watchdog callback
not being registered, thus causing the board to prematurely reset.
We already rely on gd->cyclic reliably being set to NULL by the asm
code that clears all of gd. Now that the cyclic list is a hlist, and
thus an empty list is represented by a NULL head pointer, and struct
cyclic_drv has no other members, we can just as well drop a level of
indirection and put the hlist_head directly in struct
global_data. This doesn't increase the size of struct global_data,
gets rid of an early malloc(), and generates slightly smaller code.
But primarily, this avoids having to call cyclic_init() early; the cyclic
infrastructure is simply ready to register callbacks as soon as we
enter C code.
We can still end up with schedule() being called from asm very early,
so we still need to check that gd itself has been properly initialized
[*], but once it has, gd->cyclic_list is perfectly fine to access, and
will just be an empty list.
As for cyclic_uninit(), it was never really the opposite of
cyclic_init() since it didn't free the struct cyclic_drv nor set
gd->cyclic to NULL. Rename it to cyclic_unregister_all() and use that
in test/, and also insert a call at the end of the board_init_f
sequence so that gd->cyclic_list is a fresh empty list before we enter
board_init_r().
A small piece of ugliness is that I had to add a cast in
cyclic_get_list() to silence a "discards 'volatile' qualifier"
warning, but that is completely equivalent to the existing handling of
the uclass_root_s list_head member.
[*] I'm not really sure where we guarantee that the register used for
gd contains 0 until it gets explicitly initialized, but that must be
the case, otherwise testing gd for being NULL would not make much sense.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:53 +0000 (13:50 +0200)]
cyclic: switch to using hlist instead of list
A hlist is headed by just a single pointer, so can only be traversed
forwards, and insertions can only happen at the head (or before/after
an existing list member). But each list node still consists of two
pointers, so arbitrary elements can still be removed in O(1).
This is precisely what we need for the cyclic_list - we never need to
traverse it backwards, and the order the callbacks appear in the list
should really not matter.
One advantage, and the main reason for doing this switch, is that an
empty list is represented by a NULL head pointer, so unlike a
list_head, it does not need separate C code to initialize - a
memset(,0,) of the containing structure is sufficient.
This is mostly mechanical:
- The iterators are updated with an h prefix, and the type of the
temporary variable changed to struct hlist_node*.
- Adding/removing is now just hlist_add_head (and not tail) and
hlist_del().
- struct members and function return values updated.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Currently, there is only one "user" of any of these, namely in
fs/ubifs/super.c, but that actually uses the "new-style" form, and
is (obviously, or it wouldn't have built) inside #ifndef __UBOOT__.
Before adding actual users of these, import the version as of linux
v6.1-rc1, including the hlist_entry_safe() helper used by the new
versions.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:51 +0000 (13:50 +0200)]
cyclic: drop redundant cyclic_ready flag
We're already relying on gd->cyclic being NULL before cyclic_init() is
called - i.e., we're relying on all of gd being zeroed before entering
any C code. And when we do populate gd->cyclic, its ->cyclic_ready
member is automatically set to true. So we can actually just rely on
testing gd->cyclic itself.
The only wrinkle is that cyclic_uninit() actually did set
->cyclic_ready to false. However, since it doesn't free gd->cyclic,
the cyclic infrastructure is actually still ready (i.e., the list_head
is properly initialized as an empty list).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:50 +0000 (13:50 +0200)]
cyclic: use a flag in gd->flags for recursion protection
As a preparation for future patches, use a flag in gd->flags rather
than a separate member in (the singleton) struct cyclic_drv to keep
track of whether we're already inside cyclic_run().
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
To quote the author:
The patchset adds support for the FWU Multi Bank Update[1]
feature. Certain aspects of the Dependable Boot[2] specification have
also been implemented.
The FWU multi bank update feature is used for supporting multiple
sets(also called banks) of firmware image(s), allowing the platform to
boot from a different bank, in case it fails to boot from the active
bank. This functionality is supported by keeping the relevant
information in a structure called metadata, which provides information
on the images. Among other parameters, the metadata structure contains
information on the currect active bank that is being used to boot
image(s).
Functionality is being added to work with the UEFI capsule driver in
u-boot. The metadata is read to gather information on the update bank,
which is the bank to which the firmware images would be flashed to. On
a successful completion of the update of all components, the active
bank field in the metadata is updated, to reflect the bank from which
the platform will boot on the subsequent boots.
Currently, the feature is being enabled on the STM32MP157C-DK2 and
Synquacer boards. The DK2 board boots a FIP image from a uSD card
partitioned with the GPT partioning scheme, while the Synquacer board
boots a FIP image from a MTD partitioned SPI NOR flash device.
This feature also requires changes in a previous stage of
bootloader, which parses the metadata and selects the bank to boot the
image(s) from. Support has being added in tf-a(BL2 stage) for the
STM32MP157C-DK2 board to boot the active bank images. These changes
have been merged to the upstream tf-a repository.
The patch for adding a python test for the feature has been developed,
and was sent in the version 5 of the patches[3]. However, the test
script depends on adding support for the feature on MTD SPI NOR
devices, and that is being done as part of the Synquacer
patches. Hence these set of patches do not have the test script for
the feature. That will be added through the patches for adding support
for the feauture on Synquacer platform.
Sughosh Ganu [Fri, 21 Oct 2022 12:46:08 +0000 (18:16 +0530)]
FWU: doc: Add documentation for the FWU feature
Add documentation for the FWU Multi Bank Update feature. The document
describes the steps needed for setting up the platform for the
feature, as well as steps for enabling the feature on the platform.
projects / uboot.git / log