Olof Johansson [Sun, 23 Sep 2018 13:31:04 +0000 (06:31 -0700)]
Merge tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into next/dt
TI AM654 support for v4.20 merge window.
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
* tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Olof Johansson [Sun, 23 Sep 2018 13:28:51 +0000 (06:28 -0700)]
Merge tag 'juno-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
ARMv8 Juno/Vexpress updates for v4.20
1. Enablement of scatter gather mode for CoreSight TMC-ETR routing
2. Usage of updated coresight graph bindings that eliminates loads of
dtc warnings
* tag 'juno-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Enable coresight tmc scatter gather in ETR
arm64: dts: juno: Update entries to match latest coresight bindings
Olof Johansson [Sun, 23 Sep 2018 13:28:19 +0000 (06:28 -0700)]
Merge tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux into next/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 4.20, please pull the following:
- Stefan provides a reference to the Compute Module IO Board V3 such
that we can reference the arm counterpart and still build it for arm64
- Rob fixes I2C and SPI bus warnings which are going to show up with his
update to DTC scheduled for 4.20
* tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Fix I2C and SPI bus warnings
arm64: dts: broadcom: Add reference to Compute Module IO Board V3
Olof Johansson [Sun, 23 Sep 2018 13:24:28 +0000 (06:24 -0700)]
Merge tag 'arm-soc/for-4.20/devicetree' of https://github.com/Broadcom/stblinux into next/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 4.20, please pull the following:
- Rafal updates the Broadcom BCM5301x (Northstar) DTS files to use the
new style partition parser and removes the unsupported/undocumented
linux,part-probe properties that were previously introduced
- Stefan adds supports for the Raspberry Pi Compute Module 3/3Lite, he
also updates the Raspberry Pi 3B+ USB Ethernet adapter to have proper
LED configuration
- Rob fixes a bunch of SPI bus warnings in the Northstar Plus and
Hurricane 2 DTS files
- Florian documents the Broadcom roboswitch Switch Register Access Block
(SRAB) interrupts, adds the switch interrupts to the Northstar Plus
DTS include file and finally updates the BCM958625HR reference board to
have the proper SFP module definition
* tag 'arm-soc/for-4.20/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm: Fix SPI bus warnings
ARM: dts: NSP: Wire up switch interrupts
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
ARM: dts: NSP: Enable SFP on bcm958625hr
ARM: dts: bcm283x-rpi-lan7515: Enable Ethernet LEDs
ARM: dts: BCM5301X: Specify flash partitions
ARM: dts: add Raspberry Pi Compute Module 3 and IO board
dt-bindings: bcm: Add Raspberry Pi CM3 and CM3L
Olof Johansson [Sun, 23 Sep 2018 13:20:06 +0000 (06:20 -0700)]
Merge tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
New soc support for the px30 quad-core Cortex-A35.
New boards are the px30 eval board and roc-rk3399-pc.
The rk3328 got support for the one gpio controlled via the general
register files and the rk3399 finally got its idle-states defined.
And finally fixes and improvements for firefly-rk3399 (wifi),
roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator
pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix
and type-c port supply).
* tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add type-c port supply on rk3399-sapphire board
arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64
arm64: dts: rockchip: add WiFi module support for Firefly-RK3399
arm64: dts: rockchip: remove dvs2 pinctrl from pmic on rk3399-sapphire
arm64: dts: rockchip: Fix VCC5V0_HOST_EN on rk3399-sapphire
arm64: dts: rockchip: re-order vcc_sys on rk3399-sapphire
arm64: dts: rockchip: add missing vop properties for px30
arm64: dts: rockchip: Add idle-states to device tree for rk3399
arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc
arm64: dts: rockchip: add GRF GPIO controller to rk3328
arm64: dts: rockchip: add io-domain to roc-rk3328-cc
arm64: dts: rockchip: add PX30 evaluation board devicetree
arm64: dts: rockchip: add core dtsi file for PX30 SoCs
dt-bindings: rockchip: grf: add grf and pmugrf description for px30
arm64: dts: rockchip: add support for ROC-RK3399-PC board
Olof Johansson [Sun, 23 Sep 2018 13:19:04 +0000 (06:19 -0700)]
Merge tag 'renesas-arm64-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM64 Based SoC DT Updates for v4.20
* Correct whitespace around assignments
* R-Car Gen-3 SoCs:
- Enable SDR104 for SD devices
- Include R-Car product name in DTSI files to ease maintenance
* R-Car Gen-3 SoC based boards: Convert to new LVDS DT bindings
* R-Car Gen 3 Salvator-X and Salvator-XS boards:
- Override secondary addresses of ADV748x to avoid address conflicts
* R-Car Gen 3 based Salvator-XS board: Enable SATA
* R-Car M3-N (r8a77965) SoC:
- Add FDP1 device nodes
- Move arm_cc630p and timer nodes to restore sort-order of file
- Correct clock/reset for usb2_phy1
- Correct HS-USB compat string
- Add OPPs table for cpu devices enabling CPUFreq support
- Add CAN device placeholder nodes to facilitate adding
initial device tree for KF daughter board
- Attach SYS-DMAC to the IPMMU
* R-Car M3-N (r8a77965) based ULCB board:
- Initial device tree for board and KF daughter board
* R-Car E3 (r8a77990) SoC:
- Add SYS-DMAC, I2C VIN, CSI-2, MSIOF device nodes
- Add BRG support to SCIF2 which allows an increase in serial clock accuracy
- Use CPG/MSSR and SYSC binding definitions
* R-Car E3 (r8a77990) based Ebisu board: Enable PWM
* R-Car D3 (r8a77995) SoC: Attach the SYS-DMAC to the IPMMU
* R-Car D3 (r8a77995) based Draak board: Sort device nodes
* R-Car V3H (r8a77980) based V3HSK board:
- Move lvds0 node to restore sort-order of file
* R-Car V3H (r8a77980) SoC:
- Add RWDT, CSI2 and VIN, Cortex-A53 PMU nodes
- Move IPMMU and CAN clock nodes to restore sort-order of file
* R-Car V3M (r8a77970) SoC:
- Add MMC nodes
- Move CAN clock node to restore sort-order of file
* R-Car V3M (r8a77970) based V3MSK board: Add eMMC support
* R-Car V3H (r8a77980) based Condor board: Add PCIe, DU, LVDS and HDMI support
We need to distribute out the responsibilities of the PRCMU
registers instead of having one big lump handling everything.
By making it syscon compatible, we can start grabbing the
register map elsewhere when needed.
Initial introduction of Facebook TiogaPass family equipped with
Aspeed 2500 BMC SoC. TiogaPass is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Facebook.
Specifically, This adds the TiogaPass platform device tree file
including the flash layout used by the TiogaPass BMC machines.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
Amelie Delaunay [Wed, 22 Aug 2018 09:45:00 +0000 (11:45 +0200)]
ARM: dts: stm32: update rtc st,syscfg property on stm32h743
To fit with latest rtc driver updates, rtc st,syscfg property must contain
the control register offset of pwrcfg and the mask corresponding to the
DBP (Disable Backup Protection) bit.
arm64: dts: Add devicetree for Hisilicon Hi3670 SoC
Add initial devicetree support for Hisilicon Hi3670 SoC which
is similar to Hi3660 SoC with NPU support.
This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73).
Only UART6 has been added for console support which is
pre configured by the bootloader. A fixed clock is sourcing
the UART6 which will get replaced by the clock driver when available.
arm64: dts: hisilicon: Add missing clocks property for CPUs
The clocks property should either be present for all the CPUs of a
cluster or none. If these are present only for a subset of CPUs of a
cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.
Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.
Fixes: 3a431501ec060ab368 ("arm64: dts: ti: Add Support for AM654 SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Rob Herring [Thu, 13 Sep 2018 18:12:27 +0000 (13:12 -0500)]
ARM: dts: aspeed: Fix I2C bus warnings
dtc has new checks for I2C buses. The ASpeed dts files have a node named
'i2c' which causes a false positive warning. As the node is a 'simple-bus',
correct the node name to be 'bus' to fix the warnings.
arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-ast2500-evb.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus
Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
Rob Herring [Thu, 13 Sep 2018 18:12:30 +0000 (13:12 -0500)]
ARM: dts: bcm: Fix SPI bus warnings
dtc has new checks for SPI buses. Fix the warnings in node names.
arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dtb: Warning (spi_bus_bridge): /axi@18000000/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958525er.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958525xmc.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958622hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958625hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm988312hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Rob Herring [Thu, 13 Sep 2018 18:12:42 +0000 (13:12 -0500)]
arm64: dts: broadcom: Fix I2C and SPI bus warnings
dtc has new checks for I2C and SPI buses. Fix the warnings in node names
and unit-addresses.
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@180000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@190000: node name for SPI buses should be 'spi'
Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Fri, 31 Aug 2018 19:20:39 +0000 (12:20 -0700)]
ARM: dts: NSP: Wire up switch interrupts
The Switch Register Access Block (SRAB) has one interrupt for link state
change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
and sleep timer interrupts for each management ports (5,7,8). Wire those
up so we can utilize them to speed up link resolution.
Florian Fainelli [Fri, 31 Aug 2018 19:20:38 +0000 (12:20 -0700)]
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
Document the Broadcom roboswitch Switch Register Access Block interrupt
lines and additional register base addresses for port mux configuration
and SGMII status/configuration registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
Florian Fainelli [Fri, 31 Aug 2018 19:20:37 +0000 (12:20 -0700)]
ARM: dts: NSP: Enable SFP on bcm958625hr
Enable the SFP connected to port 5 of the switch and wire up all GPIOs
to the SFP cage. Because of a hardware limitation of the i2c controller
on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
work, we use the i2c-gpio interface instead, which does not have that
limitation. This allows us to read the SFP module EEPROM, which would
not be possible otherwise since it exceeds that size during a single
read transfer.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Neil Armstrong [Thu, 13 Sep 2018 07:12:27 +0000 (09:12 +0200)]
arm64: dts: meson: Switch simple-mfd and syscon order
The order between "syscon" and "simple-mfd" is important because in these
particular cases, the node needs to be first a "simple-mfd" to expose
it's sub-nodes, and later on a "syscon" to permit other nodes to access
this register space through the "syscon" mechanism.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Takeshi Kihara [Thu, 30 Aug 2018 14:56:35 +0000 (16:56 +0200)]
arm64: dts: renesas: r8a77990: Add BRG support to SCIF2
Add the device node for the external SCIF_CLK, and describe the clock
inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2,
which can increase serial clock accuracy.
The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.
arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions
Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arm64: dts: renesas: salvator-xs: Improve SATA switch settings comments
The comments describing the non-default switch settings to use SATA are
confusing: 'Off' refers to the switch position, not to the MD12 logic
value, while the parentheses suggest otherwise. Rephrase to fix this.
Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arm64: dts: renesas: Fix whitespace around assignments
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated for a few new cases] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Eugeniu Rosca [Sun, 12 Aug 2018 13:31:49 +0000 (15:31 +0200)]
arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device tree
This is based on the existing KF device tree sources:
$ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Mon, 27 Aug 2018 18:54:35 +0000 (21:54 +0300)]
arm64: dts: renesas: condor: add PCIe support
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Mon, 27 Aug 2018 18:53:40 +0000 (21:53 +0300)]
arm64: dts: renesas: r8a77980: add PCIe support
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Fri, 24 Aug 2018 10:21:14 +0000 (11:21 +0100)]
arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
to what was done for the r8a7796 with commit a16c16a77a6b
("arm64: dts: r8a7796: Add FCPF and FCPV instances"),
commit 1e86e125c678 ("arm64: dts: renesas: r8a7796: Point
FDP1 via FCPF to IPMMU-VI0"), and commit cb44dfd14666 ("arm64:
dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0").
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 13:43:05 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores
This patch adds definitions for L2 cache for the Cortex-A53 CPU
cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57
+ 4 x Cortex-A53), and finally enables the performance monitor
unit for the Cortex-A53 cores on the R8A774A1 SoC.
Based on work done for r8a7796 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 13:43:04 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add all MSIOF nodes
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.
Based on several similar patches of the R8A7796 device tree
by Geert Uytterhoeven <geert+renesas@glider.be>
and Simon Horman <horms+renesas@verge.net.au>.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 08:58:48 +0000 (09:58 +0100)]
arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
incl. clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Thu, 23 Aug 2018 16:59:20 +0000 (19:59 +0300)]
arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support
Define the Condor/V3HSK board dependent parts of the DU and LVDS device
nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
Analog Devices ADV7511W HDMI transmitter...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Tue, 21 Aug 2018 19:50:31 +0000 (22:50 +0300)]
arm64: dts: renesas: v3msk: add eMMC support
Add the eMMC chip support for the V3M Started Kit board.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Tue, 21 Aug 2018 19:49:26 +0000 (22:49 +0300)]
arm64: dts: renesas: r8a77970: add MMC support
Define the generic R8A77970 part of the MMC0 (SDHI2) device node.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Dien Pham [Tue, 14 Aug 2018 14:12:41 +0000 (23:12 +0900)]
arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices
This patch adds OPPs table for CA57{0,1} cpu devices
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Tested-by: Simon Horman <horms+renesas@verge.net.au>
[simon: do not give nodes unit names as they have no bus addresses] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
interfaces, similar to H3, M3-W and other SoCs from the same family.
Add CAN placeholder nodes to avoid below DTC errors:
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0 not found
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1 not found
These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
Fix them beforehand.
CAN support is inspired from below commits:
- v4.7 commit c71d77200850 ("arm64: dts: r8a7795: Add CAN support")
- v4.11 commit 3ebd14011f10 ("arm64: dts: r8a7796: Add CAN support")
- v4.12 commit 8d8e85cc6286 ("arm64: dts: r8a7796: Add reset control properties")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
[simon: make placeholder minimal by only including reg property] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 20 Aug 2018 14:17:56 +0000 (23:17 +0900)]
arm64: dts: renesas: r8a77965: Attach the SYS-DMAC to the IPMMU
For R-Car M3-N hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to
IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car M3-W.
This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
projects / kernel.git / log