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3 years agodrm/amd/display: take dc_lock in short pulse handler only
Aurabindo Pillai [Wed, 19 May 2021 20:51:01 +0000 (16:51 -0400)]
drm/amd/display: take dc_lock in short pulse handler only

[Why]
Conditions that end up modifying the global dc state must be locked.
However, during mst allocate payload sequence, lock is already taken.
With StarTech 1.2 DP hub, we get an HPD RX interrupt for a reason other
than to indicate down reply availability right after sending payload
allocation. The handler again takes dc lock before calling the
dc's HPD RX handler. Due to this contention, the DRM thread which waits
for MST down reply never gets a chance to finish its waiting
successfully and ends up timing out. Once the lock is released, the hpd
rx handler fires and goes ahead to read from the MST HUB, but now its
too late and the HUB doesnt lightup all displays since DRM lacks error
handling when payload allocation fails.

[How]
Take lock only if there is a change in link status or if automated test
pattern bit is set. The latter fixes the null pointer dereference when
running certain DP Link Layer Compliance test.

Fixes: c8ea79a8a276 ("drm/amd/display: NULL pointer error during compliance test")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agoMerge tag 'amd-drm-next-5.14-2021-05-21' of https://gitlab.freedesktop.org/agd5f...
Dave Airlie [Fri, 21 May 2021 05:59:04 +0000 (15:59 +1000)]
Merge tag 'amd-drm-next-5.14-2021-05-21' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.14-2021-05-21:

amdgpu:
- RAS fixes
- SR-IOV fixes
- More BO management cleanups
- Aldebaran fixes
- Display fixes
- Support for new GPU, Beige Goby
- Backlight fixes

amdkfd:
- RAS fixes
- DMA mapping fixes
- HMM SVM fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210521045743.4047-1-alexander.deucher@amd.com
3 years agoMerge tag 'amd-drm-next-5.14-2021-05-19' of https://gitlab.freedesktop.org/agd5f...
Dave Airlie [Fri, 21 May 2021 05:29:34 +0000 (15:29 +1000)]
Merge tag 'amd-drm-next-5.14-2021-05-19' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.14-2021-05-19:

amdgpu:
- Aldebaran updates
- More LTTPR display work
- Vangogh updates
- SDMA 5.x GCR fixes
- RAS fixes
- PCIe ASPM support
- Modifier fixes
- Enable TMZ on Renoir
- Buffer object code cleanup
- Display overlay fixes
- Initial support for multiple eDP panels
- Initial SR-IOV support for Aldebaran
- DP link training refactor
- Misc code cleanups and bug fixes
- SMU regression fixes for variable sized arrays
- MAINTAINERS fixes for amdgpu

amdkfd:
- Initial SR-IOV support for Aldebaran
- Topology fixes
- Initial HMM SVM support
- Misc code cleanups and bug fixes

radeon:
- Misc code cleanups and bug fixes
- SMU regression fixes for variable sized arrays
- Flickering fix for Oland with multiple 4K displays

UAPI:
- amdgpu: Drop AMDGPU_GEM_CREATE_SHADOW flag.
  This was always a kernel internal flag and userspace use of it has always been blocked.
  It's no longer needed so remove it.
- amdkgd: HMM SVM support
  Overview: https://patchwork.freedesktop.org/series/85562/
  Porposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/tree/fxkamd/hmm-wip

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210520031258.231896-1-alexander.deucher@amd.com
3 years agoMerge tag 'drm-intel-next-2021-05-19-1' of git://anongit.freedesktop.org/drm/drm...
Dave Airlie [Thu, 20 May 2021 22:53:38 +0000 (08:53 +1000)]
Merge tag 'drm-intel-next-2021-05-19-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Core Changes:

- drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec (Jose).

Driver Changes:

- Display plane clock rates fixes and improvements (Ville).
- Uninint DMC FW loader state during shutdown (Imre).
- Convert snprintf to sysfs_emit (Xuezhi).
- Fix invalid access to ACPI _DSM objects (Takashi).
- A big refactor around how i915 addresses the graphics
  and display IP versions. (Matt, Lucas).
- Backlight fix (Lyude).
- Display watermark and DBUF fixes (Ville).
- HDCP fix (Anshuman).
- Improve cases where display is not available (Jose).
- Defeature PSR2 for RKL and ALD-S (Jose).
- VLV DSI panel power fixes and improvements (Hans).
- display-12 workaround (Jose).
- Fix modesetting (Imre).
- Drop redundant address-of op before lttpr_common_caps array (Imre).
- Fix compiler checks (Jose, Jason).
- GLK display fixes (Ville).
- Fix error code returns (Dan).
- eDP novel: back again to slow and wide link training everywhere (Kai-Heng).
- Abstract DMC FW path (Rodrigo).
- Preparation and changes for upcoming
  XeLPD display IP (Jose, Matt, Ville, Juha-Pekka, Animesh).
- Fix comment typo in DSI code (zuoqilin).
- Simplify CCS and UV plane alignment handling (Imre).
- PSR Fixes on TGL (Gwan-gyeong, Jose).
- Add intel_dp_hdcp.h and rename init (Jani).
- Move crtc and dpll declarations around (Jani).
- Fix pre-skl DP AUX precharge length (Ville).
- Remove stray newlines from random files (Ville).
- crtc->index and intel_crtc+drm_crtc pointer clean-up (Ville).
- Add frontbuffer tracking tracepoints (Ville).
- ADL-S PCI ID updates (Anand).
- Use unique backlight device names (Jani).
- A few clean-ups on i915/audio (Jani).
- Use intel_framebuffer instead of drm one on intel_fb functions (Imre).
- Add the missing MC CCS/XYUV8888 format support on display >= 12 (Imre).
- Nuke display error state (Ville).
- ADL-P initial enablement patches
  starting to land (Clint, Imre, Jose, Umesh, Vandita, Mika).
- Display clean-up around VBT and the strap bits (Lucas).
- Try YCbCr420 color when RGB fails (Werner).
- More PSR fixes and improvements (Jose).
- Other generic display code clean-up (Jose, Ville).
- Use correct downstream caps for check Src-Ctl mode for PCON (Ankit).
- Disable HiZ Raw Stall Optimization on broken gen7 (Simon).

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YKVioeu0JkUAlR7y@intel.com
3 years agoMerge tag 'drm-misc-next-2021-05-17' of git://anongit.freedesktop.org/drm/drm-misc...
Dave Airlie [Thu, 20 May 2021 03:30:27 +0000 (13:30 +1000)]
Merge tag 'drm-misc-next-2021-05-17' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for 5.14:

UAPI Changes:

Cross-subsystem Changes:

Core Changes:

 * aperture: Fix unlocking on errors

 * legacy: Fix some doc comments

Driver Changes:

 * drm/amdgpu: Free resource on fence usage query; Fix fence calculation;

 * drm/bridge: Lt9611: Add missing MODULE_DEVICE_TABLE

 * drm/i915: Print formats with %p4cc

 * drm/ingenic: IPU planes are now always of type OVERLAY

 * drm/nouveau: Remove left-over reference to struct drm_device.pdev

 * drm/panfrost: Disable devfreq if num_supplies > 1; Add Mediatek MT8183 +
   DT bindings; Cleanups

 * drm/simpledrm: Print resources with %pr; Fix use-after-free errors;
   Fix NULL deref; Fix MAINTAINERS entry

 * drm/vmwgfx: Fix memory allocation and leak in FIFO allocation; Fix
   return value in PCI resource setup

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/YKJs2IfwSYvuGPU7@linux-uq9g.fritz.box
3 years agodrm/amdgpu: stop touching sched.ready in the backend
Christian König [Tue, 18 May 2021 15:48:02 +0000 (17:48 +0200)]
drm/amdgpu: stop touching sched.ready in the backend

This unfortunately comes up in regular intervals and breaks
GPU reset for the engine in question.

The sched.ready flag controls if an engine can't get working
during hw_init, but should never be set to false during hw_fini.

v2: squash in unused variable fix (Alex)

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: fix a potential deadlock in gpu reset
Lang Yu [Mon, 17 May 2021 04:47:20 +0000 (12:47 +0800)]
drm/amd/amdgpu: fix a potential deadlock in gpu reset

When amdgpu_ib_ring_tests failed, the reset logic called
amdgpu_device_ip_suspend twice, then deadlock occurred.
Deadlock log:

[  805.655192] amdgpu 0000:04:00.0: amdgpu: ib ring test failed (-110).
[  806.290952] [drm] free PSP TMR buffer

[  806.319406] ============================================
[  806.320315] WARNING: possible recursive locking detected
[  806.321225] 5.11.0-custom #1 Tainted: G        W  OEL
[  806.322135] --------------------------------------------
[  806.323043] cat/2593 is trying to acquire lock:
[  806.323825] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.325668]
               but task is already holding lock:
[  806.326664] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.328430]
               other info that might help us debug this:
[  806.329539]  Possible unsafe locking scenario:

[  806.330549]        CPU0
[  806.330983]        ----
[  806.331416]   lock(&adev->dm.dc_lock);
[  806.332086]   lock(&adev->dm.dc_lock);
[  806.332738]
                *** DEADLOCK ***

[  806.333747]  May be due to missing lock nesting notation

[  806.334899] 3 locks held by cat/2593:
[  806.335537]  #0: ffff888100d3f1b8 (&attr->mutex){+.+.}-{3:3}, at: simple_attr_read+0x4e/0x110
[  806.337009]  #1: ffff888136b1fd78 (&adev->reset_sem){++++}-{3:3}, at: amdgpu_device_lock_adev+0x42/0x94 [amdgpu]
[  806.339018]  #2: ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.340869]
               stack backtrace:
[  806.341621] CPU: 6 PID: 2593 Comm: cat Tainted: G        W  OEL    5.11.0-custom #1
[  806.342921] Hardware name: AMD Celadon-CZN/Celadon-CZN, BIOS WLD0C23N_Weekly_20_12_2 12/23/2020
[  806.344413] Call Trace:
[  806.344849]  dump_stack+0x93/0xbd
[  806.345435]  __lock_acquire.cold+0x18a/0x2cf
[  806.346179]  lock_acquire+0xca/0x390
[  806.346807]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.347813]  __mutex_lock+0x9b/0x930
[  806.348454]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.349434]  ? amdgpu_device_indirect_rreg+0x58/0x70 [amdgpu]
[  806.350581]  ? _raw_spin_unlock_irqrestore+0x47/0x50
[  806.351437]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.352437]  ? rcu_read_lock_sched_held+0x4f/0x80
[  806.353252]  ? rcu_read_lock_sched_held+0x4f/0x80
[  806.354064]  mutex_lock_nested+0x1b/0x20
[  806.354747]  ? mutex_lock_nested+0x1b/0x20
[  806.355457]  dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.356427]  ? soc15_common_set_clockgating_state+0x17d/0x19 [amdgpu]
[  806.357736]  amdgpu_device_ip_suspend_phase1+0x78/0xd0 [amdgpu]
[  806.360394]  amdgpu_device_ip_suspend+0x21/0x70 [amdgpu]
[  806.362926]  amdgpu_device_pre_asic_reset+0xb3/0x270 [amdgpu]
[  806.365560]  amdgpu_device_gpu_recover.cold+0x679/0x8eb [amdgpu]

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Christian KÃnig <christian.koenig@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: modify system reference clock source for navi+ (V2)
Aaron Liu [Mon, 17 May 2021 09:45:35 +0000 (17:45 +0800)]
drm/amdgpu: modify system reference clock source for navi+ (V2)

Starting from Navi+, the rlc reference clock is used for system clock
from vbios gfx_info table. It is incorrect to use core_refclk_10khz of
vbios smu_info table as system clock.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: update sdma golden setting for Navi12
Guchun Chen [Mon, 17 May 2021 08:38:00 +0000 (16:38 +0800)]
drm/amdgpu: update sdma golden setting for Navi12

Current golden setting is out of date.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: update gc golden setting for Navi12
Guchun Chen [Mon, 17 May 2021 08:35:40 +0000 (16:35 +0800)]
drm/amdgpu: update gc golden setting for Navi12

Current golden setting is out of date.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Fix a use-after-free
xinhui pan [Tue, 18 May 2021 02:56:07 +0000 (10:56 +0800)]
drm/amdgpu: Fix a use-after-free

looks like we forget to set ttm->sg to NULL.
Hit panic below

[ 1235.844104] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7b4b: 0000 [#1] SMP DEBUG_PAGEALLOC NOPTI
[ 1235.989074] Call Trace:
[ 1235.991751]  sg_free_table+0x17/0x20
[ 1235.995667]  amdgpu_ttm_backend_unbind.cold+0x4d/0xf7 [amdgpu]
[ 1236.002288]  amdgpu_ttm_backend_destroy+0x29/0x130 [amdgpu]
[ 1236.008464]  ttm_tt_destroy+0x1e/0x30 [ttm]
[ 1236.013066]  ttm_bo_cleanup_memtype_use+0x51/0xa0 [ttm]
[ 1236.018783]  ttm_bo_release+0x262/0xa50 [ttm]
[ 1236.023547]  ttm_bo_put+0x82/0xd0 [ttm]
[ 1236.027766]  amdgpu_bo_unref+0x26/0x50 [amdgpu]
[ 1236.032809]  amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x7aa/0xd90 [amdgpu]
[ 1236.040400]  kfd_ioctl_alloc_memory_of_gpu+0xe2/0x330 [amdgpu]
[ 1236.046912]  kfd_ioctl+0x463/0x690 [amdgpu]

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/display: restore the backlight on modeset (v2)
Alex Deucher [Thu, 10 Dec 2020 07:30:39 +0000 (02:30 -0500)]
drm/amdgpu/display: restore the backlight on modeset (v2)

To stay consistent with the user's setting.

v2: rebase on multi-eDP support

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/display: add helper functions to get/set backlight (v2)
Alex Deucher [Tue, 11 May 2021 15:37:09 +0000 (11:37 -0400)]
drm/amdgpu/display: add helper functions to get/set backlight (v2)

And cache the value.  These can be used by the backlight callbacks
and modesetting functions.

v2: rebase on latest backlight changes.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Query correct register for DF hashing on Aldebaran
Mukul Joshi [Tue, 18 May 2021 14:58:09 +0000 (10:58 -0400)]
drm/amdgpu: Query correct register for DF hashing on Aldebaran

For Aldebaran, driver needs to query DramMegaBaseAddress to
check if DF hashing is enabled.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add video_codecs query support for aldebaran
James Zhu [Tue, 18 May 2021 12:44:23 +0000 (08:44 -0400)]
drm/amdgpu: add video_codecs query support for aldebaran

Add video_codecs query support for aldebaran.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: fix a resource leakage issue
Dennis Li [Tue, 18 May 2021 11:40:59 +0000 (19:40 +0800)]
drm/amdkfd: fix a resource leakage issue

The function kfd_lookup_process_by_pasid will increase the reference
count of kfd_process object, its caller should call kfd_unref_process to
decrease the reference count. Otherwise resource leakage will happen.

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Move dmabuf attach/detach to backend_(un)bind
Felix Kuehling [Wed, 21 Apr 2021 23:25:45 +0000 (19:25 -0400)]
drm/amdgpu: Move dmabuf attach/detach to backend_(un)bind

The dmabuf attachment should be updated by moving the SG BO to DOMAIN_CPU
and back to DOMAIN_GTT. This does not necessarily invoke the
populate/unpopulate callbacks. Do this in backend_bind/unbind instead.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Add DMA mapping of GTT BOs
Felix Kuehling [Sun, 11 Apr 2021 22:52:19 +0000 (18:52 -0400)]
drm/amdgpu: Add DMA mapping of GTT BOs

Use DMABufs with dynamic attachment to DMA-map GTT BOs on other GPUs.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Move kfd_mem_attach outside reservation
Felix Kuehling [Sun, 11 Apr 2021 22:50:23 +0000 (18:50 -0400)]
drm/amdgpu: Move kfd_mem_attach outside reservation

This is needed to avoid deadlocks with DMA buf import in the next patch.
Also move PT/PD validation out of kfd_mem_attach, that way the caller
can bo this unconditionally.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: DMA map/unmap when updating GPU mappings
Felix Kuehling [Sat, 10 Apr 2021 07:48:56 +0000 (03:48 -0400)]
drm/amdgpu: DMA map/unmap when updating GPU mappings

DMA map kfd_mem_attachments in update_gpuvm_pte. This function is called
with the BO and page tables reserved, so we can safely update the DMA
mapping.

DMA unmap when a BO is unmapped from a GPU and before updating mappings
in restore workers.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Add multi-GPU DMA mapping helpers
Felix Kuehling [Sat, 10 Apr 2021 07:43:58 +0000 (03:43 -0400)]
drm/amdgpu: Add multi-GPU DMA mapping helpers

Add BO-type specific helpers functions to DMA-map and unmap
kfd_mem_attachments. Implement this functionality for userptrs by creating
one SG BO per GPU and filling it with a DMA mapping of the pages from the
original mem->bo.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Simplify AQL queue mapping
Felix Kuehling [Fri, 9 Apr 2021 03:26:27 +0000 (23:26 -0400)]
drm/amdgpu: Simplify AQL queue mapping

Do AQL queue double-mapping with a single attach call. That will make it
easier to create per-GPU BOs later, to be shared between the two BO VA
mappings on the same GPU.

Freeing the attachments is not necessary if map_to_gpu fails. These will be
cleaned up when the kdg_mem object is destroyed in
amdgpu_amdkfd_gpuvm_free_memory_of_gpu.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Keep a bo-reference per-attachment
Felix Kuehling [Fri, 9 Apr 2021 02:27:34 +0000 (22:27 -0400)]
drm/amdgpu: Keep a bo-reference per-attachment

For now they all reference the same BO. For correct DMA mappings they will
refer to different BOs per-GPU.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Rename kfd_bo_va_list to kfd_mem_attachment
Felix Kuehling [Thu, 8 Apr 2021 23:56:12 +0000 (19:56 -0400)]
drm/amdgpu: Rename kfd_bo_va_list to kfd_mem_attachment

This name is more fitting, especially for the changes coming next to
support multi-GPU systems with proper DMA mappings. Cleaned up the code
and renamed some related functions and variables to improve readability.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: fix refcount leak
Jingwen Chen [Mon, 17 May 2021 08:16:10 +0000 (16:16 +0800)]
drm/amd/amdgpu: fix refcount leak

[Why]
the gem object rfb->base.obj[0] is get according to num_planes
in amdgpufb_create, but is not put according to num_planes

[How]
put rfb->base.obj[0] in amdgpu_fbdev_destroy according to num_planes

Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid
YuBiao Wang [Tue, 11 May 2021 10:13:02 +0000 (18:13 +0800)]
drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid

[Why]
IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it.

[How]
Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov.

Reviewed-by: Chen, Horace <Horace.Chen@amd.com>
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix typo of format termination newline
Joe Perches [Sat, 15 May 2021 17:01:26 +0000 (10:01 -0700)]
drm/amd/display: Fix typo of format termination newline

/n should be \n

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: enable idle optimizations for beige goby
Aurabindo Pillai [Fri, 7 May 2021 20:39:34 +0000 (16:39 -0400)]
drm/amd/display: enable idle optimizations for beige goby

[Why&How]
MALL requires idle optimizations to be enabled. This enables MALL
feature on dcn303

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Enable HDCP for Beige Goby
Aurabindo Pillai [Fri, 7 May 2021 19:52:01 +0000 (15:52 -0400)]
drm/amd/display: Enable HDCP for Beige Goby

[Why&How]
Add beige_goby_ta.bin to module firmware table and call psp init for TA

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Update DCN303 SR Exit Latency
Joshua Aberback [Tue, 6 Apr 2021 21:21:50 +0000 (17:21 -0400)]
drm/amd/display: Update DCN303 SR Exit Latency

[Why]
This update was made for DCN30, but it is needed for DCN303 as well

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add callback for update_soc_for_wm_a for dcn303
Aurabindo Pillai [Mon, 3 May 2021 20:15:43 +0000 (16:15 -0400)]
drm/amd/display: Add callback for update_soc_for_wm_a for dcn303

[Why&How]
Absense of this callback causes null pointer dereference.
Add the corresponding callback in dcn303 resources.

Fixes: 443dfba0248387 ("drm/amd/display: fix dcn3+ bw validation soc param update sequence")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: Enable DCN IP init for Beige Goby
Aurabindo Pillai [Wed, 10 Mar 2021 20:53:37 +0000 (15:53 -0500)]
drm/amd/amdgpu: Enable DCN IP init for Beige Goby

[Why&How]
Adds DCN IP block initialization for Beige Goby

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add DM support for Beige Goby
Aurabindo Pillai [Wed, 10 Mar 2021 20:53:11 +0000 (15:53 -0500)]
drm/amd/display: Add DM support for Beige Goby

[Why&How]

Adds the firmware definition and missing cases statement
hooks for Beige Goby support in AMDGPU DM.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Edit license info for beige goby DC files
Aurabindo Pillai [Tue, 11 May 2021 21:41:16 +0000 (17:41 -0400)]
drm/amd/display: Edit license info for beige goby DC files

[How]
* Add MIT license to all new files as SPDX tag.
* Fix copyright year

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Initial DC support for Beige Goby
Aurabindo Pillai [Mon, 15 Mar 2021 18:55:24 +0000 (14:55 -0400)]
drm/amd/display: Initial DC support for Beige Goby

[Why&How]
Add Beige Goby (DCN303) resource, irq service, & dmub loader.

v2: fix nbio include (Alex)

Signed-off-by: Chris Park <Chris.Park@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add register definitions for Beige Goby
Aurabindo Pillai [Mon, 15 Mar 2021 18:56:11 +0000 (14:56 -0400)]
drm/amd/display: Add register definitions for Beige Goby

[Why&How]
Adds registers definitions required for Beige Goby initial support.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: fix GCR_GENERAL_CNTL offset for beige_goby
Jiansong Chen [Mon, 19 Apr 2021 08:53:50 +0000 (16:53 +0800)]
drm/amdgpu: fix GCR_GENERAL_CNTL offset for beige_goby

beige_goby has similar gc_10_3 ip with sienna_cichlid,
so follow its registers offset setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: Enable gfxoff for beige_goby
Chengming Gui [Tue, 30 Mar 2021 08:26:49 +0000 (16:26 +0800)]
drm/amd/amdgpu: Enable gfxoff for beige_goby

Enable gfxoff in driver side based on SMC#73.3

v2: fix typo 'Eanble' --> 'Enable'

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Use the PPTable from VBIOS for beige_goby
Chengming Gui [Tue, 30 Mar 2021 08:22:53 +0000 (16:22 +0800)]
drm/amd/pm: Use the PPTable from VBIOS for beige_goby

Switch from softPPTable to VBIOS PPTable.

v2: drop extra parens (Alex)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add cgls for beige_goby
Tao Zhou [Thu, 22 Apr 2021 09:57:14 +0000 (17:57 +0800)]
drm/amdgpu: add cgls for beige_goby

Enable cgls to improve the runtime power efficiency.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enabled VCN3.0 CG for BEIGE GOBY
Veerabadhran Gopalakrishnan [Thu, 1 Apr 2021 13:38:39 +0000 (19:08 +0530)]
drm/amdgpu: enabled VCN3.0 CG for BEIGE GOBY

Enable VCN CG for BEIGE GOBY

Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable ih CG for beige_goby
Tao Zhou [Fri, 19 Mar 2021 06:48:28 +0000 (14:48 +0800)]
drm/amdgpu: enable ih CG for beige_goby

Enable ih clock gating for beige_goby.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable hdp CG and LS for beige_goby
Tao Zhou [Fri, 19 Mar 2021 06:44:55 +0000 (14:44 +0800)]
drm/amdgpu: enable hdp CG and LS for beige_goby

Enable hdp MGCG and LS for beige_goby.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable mc CG and LS for beige_goby
Tao Zhou [Fri, 19 Mar 2021 06:37:57 +0000 (14:37 +0800)]
drm/amdgpu: enable mc CG and LS for beige_goby

Enable mc CG and LS for beige_goby.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable athub/mmhub PG for beige_goby
Tao Zhou [Fri, 19 Mar 2021 06:29:28 +0000 (14:29 +0800)]
drm/amdgpu: enable athub/mmhub PG for beige_goby

Enable athub/mmhub power gating for beige_goby.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: support athub cg setting for beige_goby
Tao Zhou [Fri, 19 Mar 2021 06:15:28 +0000 (14:15 +0800)]
drm/amdgpu: support athub cg setting for beige_goby

Enable athub cg for beige_goby.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable GFX clock gating for beige_goby
Tao Zhou [Fri, 19 Mar 2021 06:05:34 +0000 (14:05 +0800)]
drm/amdgpu: enable GFX clock gating for beige_goby

Enable GFX MGCG, CGCG and 3DCG for beige_goby.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: use macro to get pptable members
Chengming Gui [Wed, 17 Mar 2021 09:11:53 +0000 (17:11 +0800)]
drm/amd/pm: use macro to get pptable members

Use macro to get the pptable members for different pptable structures.

v2: abstract the table operations especially get the table members
to simplify cover the two different pptable structures.
v3: move pptable operations related structures and functions into ppt.c
v4: use macro to simplify the operation to get pptable members
v5: fix parameter reference error and add dump pptable support for
beige_goby

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Evan Quan <Evan.Quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: update smu11 driver interface header for beige_goby
Chengming Gui [Wed, 17 Mar 2021 09:08:07 +0000 (17:08 +0800)]
drm/amd/pm: update smu11 driver interface header for beige_goby

Use new struct name to identify beige_goby pptable
due to extra added fields.

v2: squash in updates (Alex)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Evan Quan <Evan.Quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: add mode1 support for beige_goby
Chengming Gui [Fri, 12 Mar 2021 03:26:58 +0000 (11:26 +0800)]
drm/amd/pm: add mode1 support for beige_goby

Add mode1 reset as the default reset method for beige_goby

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: update golden_setting_10_3_5 for beige_goby
Chengming Gui [Tue, 16 Mar 2021 02:42:34 +0000 (10:42 +0800)]
drm/amd/amdgpu: update golden_setting_10_3_5 for beige_goby

add mmCGTT_SPI_{RA0/RA1}_CLK_CTRL setting

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Enable VCN for Beige Goby
Veerabadhran Gopalakrishnan [Wed, 10 Mar 2021 19:39:11 +0000 (01:09 +0530)]
drm/amdgpu: Enable VCN for Beige Goby

Enabled VCN support for Beige Goby chip

Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add gc_10_3_5 golden setting for beige_goby
Hawking Zhang [Sat, 6 Mar 2021 14:31:42 +0000 (22:31 +0800)]
drm/amdgpu: add gc_10_3_5 golden setting for beige_goby

execute gc_10_3_5 golden registers one-time initialization

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add mmhub client support for beige goby
Alex Deucher [Wed, 16 Dec 2020 15:17:20 +0000 (10:17 -0500)]
drm/amdgpu: add mmhub client support for beige goby

For decoding GPUVM page faults.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add psp support for beige_goby
Chengming Gui [Tue, 10 Nov 2020 08:02:22 +0000 (16:02 +0800)]
drm/amd/amdgpu: add psp support for beige_goby

add general PSP support for beige_goby

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add smu support for beige_goby
Chengming Gui [Tue, 3 Nov 2020 03:37:23 +0000 (11:37 +0800)]
drm/amd/amdgpu: add smu support for beige_goby

Use soft-pptable for beige_goby

v2: fix format

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: add kfd2kgd funcs for beige_goby kfd support
Chengming Gui [Wed, 21 Oct 2020 10:18:40 +0000 (18:18 +0800)]
drm/amdkfd: add kfd2kgd funcs for beige_goby kfd support

Add the function pointer.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: support beige_goby KFD
Chengming Gui [Wed, 21 Oct 2020 10:15:36 +0000 (18:15 +0800)]
drm/amdkfd: support beige_goby KFD

Add KFD support for beige_goby
v2: fix asic name typo
v3: squash in updates (Alex)
v4: squash in needs_atomics fix (Alex)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: Use IP discovery table for beige goby
Chengming Gui [Wed, 14 Oct 2020 07:51:23 +0000 (15:51 +0800)]
drm/amd/amdgpu: Use IP discovery table for beige goby

Rather than gpu info firmware.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: support cp_fw_write_wait for beige_goby
Chengming Gui [Tue, 27 Oct 2020 08:59:42 +0000 (16:59 +0800)]
drm/amd/amdgpu: support cp_fw_write_wait for beige_goby

Same as dimgrey_cavefish to support WAIT_REG_MEM packet.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add virtual display support for beige_goby
Chengming Gui [Tue, 13 Oct 2020 09:43:07 +0000 (17:43 +0800)]
drm/amd/amdgpu: add virtual display support for beige_goby

Add virtual ip block for beige_goby

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: configure beige_goby gfx according to gfx 10.3's definition
Chengming Gui [Tue, 13 Oct 2020 09:35:21 +0000 (17:35 +0800)]
drm/amd/amdgpu: configure beige_goby gfx according to gfx 10.3's definition

The gfx version of beige_goby is 10.3,
identical to sienna_cichlid,
follow the way of sienna_cichlid

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add sdma ip block for beige_goby
Chengming Gui [Tue, 13 Oct 2020 09:08:07 +0000 (17:08 +0800)]
drm/amd/amdgpu: add sdma ip block for beige_goby

Enable sdma block for beige_goby, same as sienna_cichlid

v2: share the same setting of sdma instance num with vangogh

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Suggested-by: Alexander Deucher <Alexander.Deucher@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add gfx ip block for beige_goby
Chengming Gui [Tue, 13 Oct 2020 09:04:01 +0000 (17:04 +0800)]
drm/amd/amdgpu: add gfx ip block for beige_goby

Enable gfx block for beige_goby, same as dimgrey_cavefish

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add ih ip block for beige_goby
Chengming Gui [Tue, 13 Oct 2020 08:58:01 +0000 (16:58 +0800)]
drm/amd/amdgpu: add ih ip block for beige_goby

Enable ih block for beige_goby, same as dimgrey_cavefish

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add gmc ip block for beige_goby
Chengming Gui [Tue, 13 Oct 2020 08:51:08 +0000 (16:51 +0800)]
drm/amd/amdgpu: add gmc ip block for beige_goby

Enable gmc block for beige_goby, same as sienna_cichlid

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add common ip block for beige_goby
Chengming Gui [Tue, 13 Oct 2020 08:46:21 +0000 (16:46 +0800)]
drm/amd/amdgpu: add common ip block for beige_goby

Same as dimgrey_cavefish
v2: fix comments typo

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add mmhub support for beige_goby
Chengming Gui [Tue, 13 Oct 2020 08:42:02 +0000 (16:42 +0800)]
drm/amd/amdgpu: add mmhub support for beige_goby

Same as dimgrey_cavefish

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: initialize IP offset for beige_goby
Chengming Gui [Tue, 13 Oct 2020 08:32:42 +0000 (16:32 +0800)]
drm/amd/amdgpu: initialize IP offset for beige_goby

Add ip offset definition for beige_goby and initialize it

v2: squash in fixes (Alex)
V3: fix permissions on file (Alex)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add common support for beige_goby
Chengming Gui [Tue, 13 Oct 2020 08:09:55 +0000 (16:09 +0800)]
drm/amd/amdgpu: add common support for beige_goby

Add external id and set clock gating for beige_goby

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add gmc support for beige_goby
Chengming Gui [Tue, 13 Oct 2020 07:46:16 +0000 (15:46 +0800)]
drm/amd/amdgpu: add gmc support for beige_goby

Same as dimgrey_cavefish

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add support for beige_goby firmware
Chengming Gui [Tue, 13 Oct 2020 06:48:37 +0000 (14:48 +0800)]
drm/amd/amdgpu: add support for beige_goby firmware

Add support for beige_goby cp/rlc firmware

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: set asic family and ip blocks for beige_goby
Chengming Gui [Tue, 13 Oct 2020 06:42:25 +0000 (14:42 +0800)]
drm/amd/amdgpu: set asic family and ip blocks for beige_goby

Same as navi series

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: set fw load type for beige_goby
Chengming Gui [Tue, 13 Oct 2020 06:38:49 +0000 (14:38 +0800)]
drm/amd/amdgpu: set fw load type for beige_goby

Use direct load for beige_goby

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: add beige_goby asic type
Chengming Gui [Tue, 13 Oct 2020 06:30:32 +0000 (14:30 +0800)]
drm/amd/amdgpu: add beige_goby asic type

Add chip type for beige_goby

v2: fix enum count (Alex)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: 3.2.136
Aric Cyr [Sun, 9 May 2021 19:17:58 +0000 (15:17 -0400)]
drm/amd/display: 3.2.136

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: [FW Promotion] Release 0.0.66
Anthony Koo [Sun, 9 May 2021 01:09:49 +0000 (21:09 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.66

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Refactor and add visual confirm for HW Flip Queue
Wyatt Wood [Thu, 6 May 2021 20:11:16 +0000 (16:11 -0400)]
drm/amd/display: Refactor and add visual confirm for HW Flip Queue

[Why]
Visual confirm will indicate if driver is programming
the surface address.
Refactor is required because much of the visual confirm
logic is buried deep in the mpcc files.
In addition, visual confirm is not updated during fast updates.

[How]
In order to have visual confirm for driver flips, visual confirm
needs to be updated on every frame, including fast updates.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.

v2: drop unused variable (Alex)

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Use the correct max downscaling value for DCN3.x family
Nikola Cornij [Fri, 7 May 2021 02:46:52 +0000 (22:46 -0400)]
drm/amd/display: Use the correct max downscaling value for DCN3.x family

[why]
As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The
max downscaling limit value for DCN2.x is 250, which means it's
calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167.

[how]
Set maximum downscaling limit to 167 for DCN3.x

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Avoid get/put vblank when stream disabled
Wayne Lin [Wed, 28 Apr 2021 10:04:44 +0000 (18:04 +0800)]
drm/amd/display: Avoid get/put vblank when stream disabled

[Why]
amdgpu_dm_crtc_set_crc_source() will call
amdgpu_dm_crtc_configure_crc_source() to enable/disable CRC
generation. However, configuration will be deferred to stream enabled.
If stream is not enabled, current flow will still try to get/put vblank
refcount.

[How]
Return EINVAL to skip actions on vblank refcount when stream is not
enabled.

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Chao-kai Wang <Stylon.Wang@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Correct DPCD revision for eDP v1.4
Zhan Liu [Wed, 5 May 2021 21:44:46 +0000 (17:44 -0400)]
drm/amd/display: Correct DPCD revision for eDP v1.4

[Why]
eDP version and DPCD revision are different. Per VESA
spec, "The DPCD revision for eDP v1.4 is 13h".

SUPPORTED_LINK_RATES is valid since eDP v1.4 (DPCD_REV_13).

[How]
Correct DPCD_REV for eDP v1.4.

Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add Overflow check to skip MALL
Bhawanpreet Lakha [Thu, 29 Apr 2021 20:32:47 +0000 (16:32 -0400)]
drm/amd/display: Add Overflow check to skip MALL

[Why]
In some small modes (<200pixels) the stutter period is really big and will cause
overflow. In these cases we shouldnt try to enable MALL as it will exceeds range
of hysteresis timer (this can be seen in some IGT tests where the
plane size is small)

[How]
Compare the stutter_period with the frame time and if we will overflow
there is no point in trying to enable MALL (and see the ASSERT) so we
early exist in this case

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Refactor suspend/resume of Secure display
Wayne Lin [Tue, 27 Apr 2021 04:00:40 +0000 (12:00 +0800)]
drm/amd/display: Refactor suspend/resume of Secure display

[Why]
Once set ROI and do suspend/resume, current flow will not enable
OTG_CRC_CTL again due to we'll defer crc configuration when stream
is enabled.

[How]
Remove current suspend/resume function and have logic implemented into
amdgpu_dm_atomic_commit_tail()

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Chao-kai Wang <Stylon.Wang@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: consider channel coding in configure lttpr mode
Wenjing Liu [Mon, 3 May 2021 22:42:28 +0000 (18:42 -0400)]
drm/amd/display: consider channel coding in configure lttpr mode

[why]
Some lttpr configuration steps are exclusive to 8b/10b channel
coding mode. We need to take channel conding into account.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Acked-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: rename perform_link_training_int function
Wenjing Liu [Mon, 3 May 2021 21:32:05 +0000 (17:32 -0400)]
drm/amd/display: rename perform_link_training_int function

[why]
The function's name doesn't represent what it actaully does.
The function implements necessary steps for our hardware to
transition from link training mode back to video idle mode.
Therefore, rename the function as dp_transition_to_video_idle
so everyone can understand it.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: decide link training settings based on channel coding
Wenjing Liu [Mon, 3 May 2021 21:05:40 +0000 (17:05 -0400)]
drm/amd/display: decide link training settings based on channel coding

[how]
Rename initialize_training_settings to decide_training_settings.
Call get link encoding format and decide training settings
based on current channel coding.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: determine dp link encoding format from link settings
Wenjing Liu [Mon, 3 May 2021 18:51:27 +0000 (14:51 -0400)]
drm/amd/display: determine dp link encoding format from link settings

[how]
Implement a function that determines link encoding format
based on the link settings passed in.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Disconnect non-DP with no EDID
Chris Park [Tue, 4 May 2021 20:20:55 +0000 (16:20 -0400)]
drm/amd/display: Disconnect non-DP with no EDID

[Why]
Active DP dongles return no EDID when dongle
is connected, but VGA display is taken out.
Current driver behavior does not remove the
active display when this happens, and this is
a gap between dongle DTP and dongle behavior.

[How]
For active DP dongles and non-DP scenario,
disconnect sink on detection when no EDID
is read due to timeout.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Minor refactor of DP PHY test automation
George Shen [Tue, 4 May 2021 19:31:37 +0000 (15:31 -0400)]
drm/amd/display: Minor refactor of DP PHY test automation

[Why]
Improve readability and maintainability of code.

[How]
Refactor test pattern size calculation out of function
call parameter and store value in variable.

Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Document set RECOUT operation
Rodrigo Siqueira [Tue, 4 May 2021 14:09:25 +0000 (10:09 -0400)]
drm/amd/display: Document set RECOUT operation

During the investigation on how to add visual confirmation on top of the
planes used by DCN, it becomes evident that the lack of information in
the code makes this work unnecessarily complicated. This commit
introduces a set of documentation related to the RECOUT operation in
order to make it easy for developers to navigate this set of functions.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add kernel-doc to some hubp functions
Rodrigo Siqueira [Thu, 15 Apr 2021 14:22:03 +0000 (10:22 -0400)]
drm/amd/display: Add kernel-doc to some hubp functions

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Remove legacy comments
Rodrigo Siqueira [Thu, 15 Apr 2021 13:57:19 +0000 (09:57 -0400)]
drm/amd/display: Remove legacy comments

To improve the code readability, this commit removes a set of commented
and not used functions for a long time. Notice that now we have the
amdgpu_dm_dtn_log, which prints all the relevant information that we
need.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add documentation for power gate plane
Rodrigo Siqueira [Thu, 15 Apr 2021 13:32:57 +0000 (09:32 -0400)]
drm/amd/display: Add documentation for power gate plane

This commit introduces kernel documentation to some essential functions
related to power gate control over planes. It also adds a macro to make
one part of the code easy to understand.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add get_current_time interface to dmub_srv
Wyatt Wood [Tue, 19 Jan 2021 22:05:05 +0000 (17:05 -0500)]
drm/amd/display: Add get_current_time interface to dmub_srv

[Why]
Need to get current DMUB time.

[How]
Add get_current_time interface to dmub_srv.

v2: drop whitespace changes (Alex)

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: treat memory as a single-channel for asymmetric memory V3
Hugo Hu [Wed, 21 Apr 2021 06:23:44 +0000 (14:23 +0800)]
drm/amd/display: treat memory as a single-channel for asymmetric memory V3

Previous patch caused crash and had been reverted. This patch
addresses the issue without regression.

[Why]
1. Driver use umachannelnumber to calculate watermarks for stutter.
In asymmetric memory config, the actual bandwidth is less than
dual-channel. The bandwidth should be the same as single-channel.
2. We found single rank dimm need additional delay time for stutter.

[How]
Get information from each DIMM. Treat memory config as a single-channel
for asymmetric memory in bandwidth calculating.
Add additional delay time for single rank dimm.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Reset max GFX clock after disabling determinism
Lijo Lazar [Thu, 13 May 2021 08:21:23 +0000 (16:21 +0800)]
drm/amd/pm: Reset max GFX clock after disabling determinism

When determinism mode is disabled on aldebaran, max GFX clock will
be reset to default max frequency value.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Fix showing incorrect frequencies on aldebaran
Lijo Lazar [Thu, 13 May 2021 07:51:18 +0000 (15:51 +0800)]
drm/amd/pm: Fix showing incorrect frequencies on aldebaran

v1: Use the current and custom pstate frequencies to track the current and
user-set min/max values in manual and determinism mode. Previously, only
actual_* value was used to track the currrent and user requested value.
The value will get reassigned whenever user requests a new value with
pp_od_clk_voltage node. Hence it will show incorrect values when user
requests an invalid value or tries a partial request without committing
the values. Separating out to custom and current variable fixes such
issues.

v2: Remove redundant if-else check

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Add custom/current freq to pstates
Lijo Lazar [Thu, 13 May 2021 06:42:17 +0000 (14:42 +0800)]
drm/amd/pm: Add custom/current freq to pstates

Add custom member for user requested custom frequency, level mask
or min/max frequencies. Add curr member to keep track of the current
active values.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Conditionally reset RAS counters on boot
John Clements [Mon, 17 May 2021 08:36:26 +0000 (16:36 +0800)]
drm/amdgpu: Conditionally reset RAS counters on boot

Only clear RAS error counters if perestent EDC harvesting is not supported

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang
Changfeng [Fri, 14 May 2021 07:28:25 +0000 (15:28 +0800)]
drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang

There is problem with 3DCGCG firmware and it will cause compute test
hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid
compute hang.

Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>