Boyan Karatotev [Mon, 9 Jan 2023 11:50:24 +0000 (11:50 +0000)]
build(docs): update Python dependencies
Update the python dependencies for building the project's Sphinx
documentation. Sphinx plugins are updated to the latest version, while
Sphinx itself is only updated to 5.3.0 (latest 5.x.x revision) due to
sphinx-rtd-theme not supporting any higher (both require incompatible
versions of docutils). Myst-parser is also updated to the latest version
to prevent a docutils clash as well.
The effect of this is to bump certifi to version 2022.12.7 and wheel to
0.38.4 as suggested by dependabot.
Boyan Karatotev [Thu, 9 Feb 2023 15:59:39 +0000 (15:59 +0000)]
fix(docs): make required compiler version == rather than >=
TF-A carries its own compiler-rt so higher versions of the compilers may
not necessarily work. Because TF-A is only tested on the specified
versions in the CI, any breakage remains unknown. Update the
prerequisites guide to make it more apparent that this is the case.
Boyan Karatotev [Thu, 9 Feb 2023 15:55:34 +0000 (15:55 +0000)]
fix(deps): add missing aeabi_memset.S
This file provides __aeabi_memclr8 builtin which the Ubuntu 22.04
version of clang 14 needs to compile. Add it to prevent this oddity from
failing the build.
Thomas Viehweger [Mon, 23 Jan 2023 10:26:37 +0000 (11:26 +0100)]
fix(tsp): loop / crash if mmap of region fails
In test_memory_send the variable i is of unsigned type, so
it is never negative. If i is 0, the result of i-- is 4294967295. Don't know what happens if trying to
access composite->address_range_array[4294967295].
Made i a signed integer.
Signed-off-by: Thomas Viehweger <Thomas.Viehweger@rohde-schwarz.com>
Change-Id: I8b4e532749b5e86e4b5acd238e72c3f88e309ff2
Merge changes from topic "mb/tos-fw-config-load-refactor" into integration
* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW config
refactor(fvp): rename the DTB info structure member
feat(fconf): rename 'ns-load-address' to 'secondary-load-address'
There were some late comments to the prior change (18635) which are
address in this commit. There was also an invalid return value check
which was changed and the wrong result was being returned via the SMC
call for loading OP-TEE which is now fixed.
laurenw-arm [Wed, 8 Feb 2023 19:14:54 +0000 (13:14 -0600)]
fix(cert-create): change WARN to VERBOSE
SAVE_KEYS is set to '0' by default, causing cert_create to
show the 'Key filename not specified' message on each run
even though this is perfectly normal. Show the message only
in the VERBOSE log level.
Maksims Svecovs [Thu, 9 Feb 2023 16:48:34 +0000 (16:48 +0000)]
feat(git-hooks): add pre-commit hook
Adds a pre-commit git hook to keep track of copyright year.
Checks staged files for Arm copyright header and suggests a change if
the year is outdated. Works with both single-year format and
from_year-to_year format.
The tos_fw_config is currently loaded into memory by BL2 and
consumed by SPMD (part of BL31) and BL32 firmwares. This does
not work in RME-enabled systems as BL31 uses the root PAS memory
and does not trust secure PAS memory.
A first attempt was made to map the TOS_FW_CONFIG region as root PAS,
and then to remap to secure PAS after SPMD consumption, but this was
not suitable for RME systems where memory encryption is enabled.
This can be solved by copying the TOS FW config (SPMC manifest) from
the Root PAS region to the Secure PAS region so that BL32 can consume
it.
Change-Id: I8eef8345366199cb0e367db883c34a5b5136465d Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Maksims Svecovs [Thu, 2 Feb 2023 16:10:22 +0000 (16:10 +0000)]
fix(context-mgmt): enable SCXTNUM access
Enable SCXTNUM_ELx access for lower ELs in non-secure state.
Make realm context setup take this build flag into account but enable it
by default when RME is used.
Merge changes I7bd311d7,Iea7dcfe3,I9d890934 into integration
* changes:
refactor(allwinner): use fdt_node_is_enabled() in AXP driver
fix(allwinner): check RSB availability in DT on H6
refactor(fdt): introduce common fdt_node_is_enabled()
laurenw-arm [Thu, 11 Aug 2022 20:29:56 +0000 (15:29 -0500)]
feat(psa): interface with RSS for NV counters
Adding AP/RSS interface for retrieving and incrementing non-volatile
counters.
The read interface implements the psa_call:
psa_call(RSS_PLATFORM_SERVICE_HANDLE,
RSS_PLATFORM_API_ID_NV_READ,
in_vec, 1, out_vec, 1);
where the in_vec indicates which of the 3 counters we want, and the
out_vec stores the counter value we get back from RSS.
The increment interface implements the psa_call:
psa_call(RSS_PLATFORM_SERVICE_HANDLE,
RSS_PLATFORM_API_ID_NV_INCREMENT,
in_vec, 1, (psa_outvec *)NULL, 0);
where, again, in_vec indicates the counter to increment, and we don't
get any output parameter from RSS.
Through this service, we will be able to get/increment any of the 3 NV
counters used on a CCA platform:
- NV counter for CCA firmware (BL2, BL31, RMM).
- NV counter for secure firmware.
- NV counter for non-secure firmware.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Signed-off-by: Raef Coles <raef.coles@arm.com>
Change-Id: I4c1c7f4837ebff30de16bb0ce7ecd416b70b1f62
feat(fvp): update device tree with load addresses of TOS_FW config
Provided both the root and secure addresses for TOS_FW config
in case of RME enabled systems where root address is in Root
SRAM and secure address is in Trusted DRAM.
Non-RME systems are unaffected by this change.
Change-Id: Ifb927c90fa5a68fe5362980858b4ddc5403ac95b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
feat(fconf): rename 'ns-load-address' to 'secondary-load-address'
The 'ns-load-address' property has been renamed to 'secondary-load-
address' in order to make it more generic. It can be used to copy
the configuration to any location, be it root, secure, or non-secure.
Change-Id: I122508e155ccd99082296be3f6b8db2f908be221 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Andre Przywara [Wed, 1 Feb 2023 22:28:37 +0000 (22:28 +0000)]
fix(allwinner): check RSB availability in DT on H6
At the moment we access the RSB bus on all Allwinner H6 boards
unconditionally, even though some boards do not have any PMIC at all,
while others have some I2C devices connected to the same pins.
The latter case is just fragile, but the first case leads to a hang on
at least one board, as reported by Jernej.
Scan the devicetree, to check for the availability of the RSB bus node.
Proceed only if the RSB DT node is actually enabled.
Change-Id: Iea7dcfe3e085e173334d098ec4ddcb6c4b085771 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Fri, 3 Feb 2023 11:11:18 +0000 (11:11 +0000)]
refactor(fdt): introduce common fdt_node_is_enabled()
There are several users in the tree which want to check whether a given
FDT node is enabled or not: the "status" property holds that
information. So far all those users provide private implementations,
some of them having issues.
Export a generic implementation of that function in fdt_wrappers.h, as
a "static inline" function to not increase code size.
Also replace the existing implementation in Arm's fconf code, which had
a tiny bug in needlessly using the property length:
"status = [6f 6b 61 79 20];" would pass the check, where it should not.
The proper solution is also simpler: status must be a string, and
strings must be NUL-terminated in a DT. strcmp() would terminate on the
first NUL in *either* of the two strings it compares, so it would never
walk beyond the property boundary in the DTB.
Change-Id: I9d89093432f127c09add6cf5c93a725bc534e5de Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Soby Mathew [Wed, 1 Feb 2023 16:03:22 +0000 (17:03 +0100)]
Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration
* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data
Jay Buddhabhatti [Tue, 24 Jan 2023 07:32:35 +0000 (23:32 -0800)]
fix(versal-net): populate gic v3 rdist data statically
Currently gicv3_rdistif_probe() is called per CPU. In case of maxcpus=1,
only 1 core is initialized and gicr_base_addrs initialized for CPU 0
only. Because of this assertion is raised during Linux system suspend.
During Linux suspend, platform callback saves GIC v3 state which
internally invokes arm_gicv3_distif_pre_save(). This function tries to use
gicr_base for all CPUs. Since GICR base address for secondary CPUs are not
initialized, it raises assertion.
To fix the issue, populate GIC v3 rdist data statically (similar to Versal)
instead of dynamically initializing GIC v3 rdist per CPU.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I98c97c03e451d05f4ebac358e197617ab9d9b71f
Akshay Belsare [Wed, 18 Jan 2023 10:24:12 +0000 (15:54 +0530)]
feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.
This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be utilized on platforms that can ensure security is maintained up
until the point the SMC is invoked as it breaks the normal barrier
between the secure and non-secure world.
AlexeiFedorov [Thu, 29 Dec 2022 15:57:40 +0000 (15:57 +0000)]
feat(rme): read DRAM information from FVP DTB
This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.
Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning
Loic Poulain [Wed, 11 Jan 2023 15:08:48 +0000 (16:08 +0100)]
perf(imx): speed-up console/uart TX using FIFO
The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taking benefit of the 32-byte FIFO.
We then need to implement the flush function to be sure the
transmit is complete (FIFO and shift register empty).
Davidson K [Fri, 13 Jan 2023 08:32:13 +0000 (14:02 +0530)]
feat(plat/tc): enable MPAM functionality of L3 DSU cache
The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are accessed through utility bus of DSU that are memory mapped from
0x1_0000_1000.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20
Harrison Mutai [Fri, 9 Dec 2022 12:14:25 +0000 (12:14 +0000)]
fix(cpus): workaround for Cortex-A510 erratum 2684597
Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
workaround is to execute a TSB CSYNC and DSB before executing WFI for
power down.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873361/latest
https://developer.arm.com/documentation/SDEN1873351/latest
Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Merge changes from topic "fix_misra_partition_mmc" into integration
* changes:
fix(mmc): align part config type
fix(mmc): do not modify r_data in mmc_send_cmd()
fix(mmc): explicitly check operators precedence
fix(partition): add U suffix for unsigned numbers
fix(partition): add missing curly braces
Harrison Mutai [Wed, 11 Jan 2023 17:01:04 +0000 (17:01 +0000)]
fix(psci): tighten psci_power_down_wfi behaviour
A processing element should never return from a wfi, however, due to a
hardware bug, certain CPUs may wake up because of an external event.
This patch tightens the behaviour of the common power down sequence, it
ensures the routine never returns by entering a wfi loop at its end. It
aligns with the behaviour of the platform implementations.
Change-Id: I36d8b0c64eccb71035bf164b4cd658d66ed7beb4 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Rohit Mathew [Fri, 11 Nov 2022 18:45:11 +0000 (18:45 +0000)]
fix(mpam): run-time checks for mpam save/restore routines
With "ENABLE_MPAM_FOR_LOWER_ELS" and "CTX_INCLUDE_EL2_REGS" build
options enabled, MPAM EL2 registers would be saved/restored as part of
context management. Context save/restore routines as of now would
proceed to access all of MPAM EL2 registers without any runtime checks.
MPAM specification states that MPAMHCR_EL2 should only be accessed if
MPAMIDR_EL1.HAS_HCR is "1". Likewise, MPAMIDR_EL1.VPMR_MAX has to be
probed to obtain the maximum supported MPAMVPM<x>_EL2 before accessing
corresponding MPAMVPM<x>_EL2 registers. Since runtime checks are not
being made, an exception would be raised if the platform under test
doesn't support one of the registers. On Neoverse reference design
platforms, an exception is being raised while MPAMVPM2_EL2 or above are
accessed. Neoverse reference design platforms support only registers
till MPAMVPM1_EL2 at this point.
To resolve this, add sufficient runtime checks in MPAM EL2 context
save/restore routines. As part of the new save/restore routines,
MPAMIDR_EL1.HAS_HCR and MPAMIDR_EL1.VPMR_MAX are probed for the right
set of registers to be saved and restored.
Antonio Borneo [Thu, 22 Sep 2022 10:15:27 +0000 (12:15 +0200)]
feat(fiptool): handle FIP in a disk partition
When FIP is programmed in a disk partition, fiptool cannot be used
directly; this forces the user to temporarily copy the partition
to a file, apply fiptool and copy back the file. This is caused by
fstat() that returns zero file size on a block special file, thus
making fiptool commands info, update, unpack and remove to exit.
For either Linux host or Linux target, recover the partition size
with ioctl() and use it as FIP file size. E.g.:
fiptool info /dev/disk/by-partlabel/fip-a
fiptool info /dev/mtdblock4
While there, rework two identical error log messages to provide
more details about the failure and update the date in copyright.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I7cab60e577422d94c24ba7e39458f58bcebc2336
Merge changes from topic "fix_sparse_warnings" into integration
* changes:
fix(libc): remove __putchar alias
fix(console): correct scopes for console symbols
fix(auth): use NULL instead of 0 for pointer check
fix(io): compare function pointers with NULL
fix(fdt-wrappers): use correct prototypes
Manish Pandey [Thu, 19 Jan 2023 17:19:50 +0000 (18:19 +0100)]
Merge changes from topic "feat_state_rework" into integration
* changes:
feat(fvp): enable FEAT_HCX by default
refactor(context-mgmt): move FEAT_HCX save/restore into C
refactor(cpufeat): convert FEAT_HCX to new scheme
feat(fvp): enable FEAT_FGT by default
refactor(context-mgmt): move FEAT_FGT save/restore code into C
refactor(amu): convert FEAT_AMUv1 to new scheme
refactor(cpufeat): decouple FGT feature detection and build flags
refactor(cpufeat): check FEAT_FGT in a new way
refactor(cpufeat): move helpers into .c file, rename FEAT_STATE_
feat(aarch64): make ID system register reads non-volatile
Bipin Ravi [Wed, 18 Jan 2023 17:03:21 +0000 (11:03 -0600)]
fix(cpus): workaround for Cortex-A78C erratum 2772121
Cortex-A78C erratum 2772121 is a Cat B erratum that applies to
all revisions <=r0p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.
Waleed Elmelegy [Mon, 16 Jan 2023 15:10:38 +0000 (15:10 +0000)]
fix(plat/css): fix invalid redistributor poweroff
Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf
introduced an invalid redistributor power off
where we turn off the redistributor without
checking if the system power domain level is
turning off, otherwise we can turn off a
redistributor when other cores or clusters are
sharing it, also if it does indeed needs
powering off during suspend we do it twice.
This change fixes this by checking on the
system power state first then turning off
the redistributor.
Manish Pandey [Wed, 18 Jan 2023 11:06:11 +0000 (12:06 +0100)]
Merge changes from topic "mtk_spm" into integration
* changes:
refactor(mediatek): add new LPM API for further extension
refactor(mediatek): change the parameters of LPM API
refactor(mediatek): change LPM header file path for further extension
feat(mt8188): keep infra and peri on when system suspend
feat(mt8188): enable SPM and LPM
feat(mt8188): add SPM feature support
feat(mt8188): add MT8188 SPM support
feat(mediatek): add SPM's SSPM notifier
feat(mt8188): add the register definitions accessed by SPM
feat(mediatek): add new features of LPM
Michal Simek [Wed, 18 Jan 2023 07:55:20 +0000 (08:55 +0100)]
fix(zynqmp): fix xck24 silicon ID
Origin ID code has changed from origin description. After receiving part
new ID code come up that's why fix it. The origin ID code has been added
by commit 86869f99d0c1 ("feat(zynqmp): add support for xck24 silicon").
Change-Id: I727bfe43fd7ef9e604f63bde5fa37fa3666db8c4 Signed-off-by: Michal Simek <michal.simek@amd.com>
Manish Pandey [Tue, 17 Jan 2023 16:43:29 +0000 (17:43 +0100)]
Merge changes from topic "st_dt_update" into integration
* changes:
refactor(stm32mp15-fdts): remove unused PMIC nodes
fix(stm32mp15-fdts): use interrupts-extended for i2c2
style(stm32mp15-fdts): remove extra spaces on vbus
AlexeiFedorov [Wed, 14 Dec 2022 17:28:11 +0000 (17:28 +0000)]
feat(rme): set DRAM information in Boot Manifest platform data
This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manifest' is extended with 'plat_dram' structure
which contains information about platform's DRAM layout:
- number of DRAM banks;
- pointer to 'dram_bank[]' array;
- check sum: two's complement 64-bit value of the sum of
data in 'plat_dram' and 'dram_bank[] array.
Each 'dram_bank' structure holds information about DRAM
bank base address and its size. This values must be aligned
to 4KB page size.
The patch increases Boot Manifest minor version to 2 and
removes 'typedef rmm_manifest_t' as per
"3.4.15.1. Avoid anonymous typedefs of structs/enums in headers" of
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html
Merge changes from topic "ti-k3-checks-and-refactor" into integration
* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function
refactor(ti): use console_set_scope() rather than empty function hack
refactor(ti): factor out common board code into common files
feat(ti): add PSCI system_off support
feat(ti): do not handle EAs in EL3
feat(ti): set snoop-delayed exclusive handling on A72 cores
feat(ti): disable L2 dataless UniqueClean evictions
feat(ti): set L2 cache ECC and and parity on A72 cores
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
Manish Pandey [Mon, 16 Jan 2023 15:44:17 +0000 (16:44 +0100)]
Merge changes from topic "refactor_st_common" into integration
* changes:
refactor(st): move board info in common code
refactor(st): move GIC code to common directory
refactor(st): move boot backup register management
Andrew Davis [Tue, 27 Sep 2022 12:13:21 +0000 (07:13 -0500)]
feat(ti): do not handle EAs in EL3
This could be useful if we had extra information to print or
when RAS extensions are available, neither apply here so lets
not trap these in EL3 for now.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ia0334eb845686964e794afe45c7777ea64fd6b0b
Andrew Davis [Thu, 12 Jan 2023 15:32:33 +0000 (09:32 -0600)]
feat(ti): set snoop-delayed exclusive handling on A72 cores
Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.
TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.
As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9
Andrew Davis [Tue, 10 Jan 2023 19:14:37 +0000 (13:14 -0600)]
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883
Tony K Nadackal [Wed, 24 Nov 2021 16:09:26 +0000 (16:09 +0000)]
feat(rdn2): add platform id value for rdn2 variant 3
The RD-N2-Cfg3 platform is a variant of the RD-N2 platform with the
significant difference being the number of ITS blocks and the use of a
different part number.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: Id4c5faeae44f21da79cb59540558192d0b02b124
Tony K Nadackal [Sat, 12 Nov 2022 23:21:20 +0000 (23:21 +0000)]
refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag
The core count is one of the significant difference between the various
RD-N2 platform variants. The PLAT_ARM_CLUSTER_COUNT macro defines the
number of core/cluster for a variant. In preparation to add another
variant of RD-N2 platform, replace the use of CSS_SGI_PLATFORM_VARIANT
build flag, where applicable, with the PLAT_ARM_CLUSTER_COUNT macro.
This helps to reduce the changes required to add support for a new
variant.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I89b168308d1b5f7edd402205dd25d6c3a355e100
Joanna Farley [Thu, 12 Jan 2023 10:11:28 +0000 (11:11 +0100)]
Merge changes from topic "fix-power-up-dwn-issue" into integration
* changes:
fix(versal-net): enable wake interrupt during client suspend
fix(versal-net): disable wakeup interrupt during client wakeup
fix(versal-net): clear power down bit during wakeup
fix(versal-net): fix setting power down state
fix(versal-net): clear power down interrupt status before enable
fix(versal-net): resolve misra rule 20.7 warnings
fix(versal-net): resolve misra 10.6 warnings
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