Noralf Trønnes [Tue, 31 Jan 2017 15:05:57 +0000 (16:05 +0100)]
dt-bindings: display/panel: Add common rotation property
Display panels can be oriented many ways, especially in the embedded
world. The rotation property is a way to describe this orientation.
The counter clockwise direction is chosen because that's what fbdev
and drm use.
Dave Airlie [Fri, 17 Feb 2017 20:35:25 +0000 (06:35 +1000)]
Merge tag 'drm-intel-next-fixes-2017-02-17' of git://anongit.freedesktop.org/git/drm-intel into drm-next
i915 and GVT fixes for v4.11 merge window
* tag 'drm-intel-next-fixes-2017-02-17' of git://anongit.freedesktop.org/git/drm-intel: (32 commits)
drm/i915: Fix not finding the VBT when it overlaps with OPREGION_ASLE_EXT
drm/i915: Pass timeout==0 on to i915_gem_object_wait_fence()
drm/i915/gvt: Disable access to stolen memory as a guest
drm/i915: Avoid spurious WARNs about the wrong pipe in the PPS code
drm/i915: Check for timeout completion when waiting for the rq to submitted
drm/i915: A hotfix for making aliasing PPGTT work for GVT-g
drm/i915: Restore context and pd for ringbuffer submission after reset
drm/i915: Let execlist_update_context() cover !FULL_PPGTT mode.
drm/i915/lspcon: Fix resume time initialization due to unasserted HPD
drm/i915/gen9+: Enable hotplug detection early
drm/i915: Reject set-tiling-ioctl with stride==0 and a tiling mode
drm/i915: Recreate internal objects with single page segments if dmar fails
drm/i915/gvt: return error code if dma map iova failed
drm/i915/gvt: optimize the inhibit context mmio load
drm/i915/gvt: add sprite plane flip done support.
drm/i915/gvt: add missing display part reset for vGPU reset
drm/i915/gvt: Fix shadow context descriptor
drm/i915/gvt: Fix alignment for GTT allocation
drm/i915/gvt: fix crash at function release_shadow_wa_ctx
drm/i915/gvt: enable IOMMU for gvt
...
Dave Airlie [Fri, 17 Feb 2017 07:43:07 +0000 (17:43 +1000)]
Merge branch 'linux-4.11' of git://github.com/skeggsb/linux into drm-next
- Rework of the secure boot code, in preparation for GP10x secure boot.
- Improvements to channel recovery
- Initial power budget code
- Some preparation for an upcoming MMU rework (probably 4.12)
- Misc other fixes.
* 'linux-4.11' of git://github.com/skeggsb/linux: (88 commits)
drm/nouveau/tmr: provide backtrace when a timeout is hit
drm/nouveau/pci/g92: Fix rearm
drm/nouveau/drm/therm/fan: add a fallback if no fan control is specified in the vbios
drm/nouveau/hwmon: expose power_max and power_crit
drm/nouveau/iccsense: Parse max and crit power level
drm/nouveau/bios/power_budget: Add basic power budget parsing
drm/nouveau/fifo/gk104-: preempt recovery
drm/nouveau/fifo/gk104-: trigger mmu fault before attempting engine recovery
drm/nouveau/fifo/gk104-: ACK SCHED_ERROR before attempting CTXSW_TIMEOUT recovery
drm/nouveau/fifo/gk104-: directly use new recovery code for ctxsw timeout
drm/nouveau/fifo/gk104-: directly use new recovery code for mmu faults
drm/nouveau/fifo/gk104-: reset all engines a killed channel is still active on
drm/nouveau/fifo/gk104-: refactor recovery code
drm/nouveau/fifo/gk104-: better detection of chid when parsing engine status
drm/nouveau/fifo/gk104-: separate out engine status parsing
drm/nouveau/fifo: add an api for initiating channel recovery
drm/nouveau/top: add function to translate subdev index to mmu fault id
drm/nouveau/gr/gf100-: implement chsw_load() method
drm/nouveau/gr: implement chsw_load() method
drm/nouveau/core: add engine method to assist in determining chsw direction
...
g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm.
Reported-by: Andrew Randrianasulu <randrianasulu@gmail.com> Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
Karol Herbst [Mon, 23 Jan 2017 22:10:11 +0000 (23:10 +0100)]
drm/nouveau/bios/power_budget: Add basic power budget parsing
v2: Set entry to 0xff if not found
Add cap entry for ver 0x30 tables
Rework to fix memory leak
v3: More error checks
Simplify check for invalid entries
v4: disable for ver 0x10 for now
move assignments after the second last return
Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 18 Jan 2017 05:37:24 +0000 (15:37 +1000)]
drm/nouveau/fifo/gk104-: trigger mmu fault before attempting engine recovery
Greatly improves the chances of recovering the GPU from a CTXSW_TIMEOUT.
Tested with piglit's arb_shader_image_load_store-atomicity, which causes
GR to hang in such a way that recovery failed (CTXSW_TIMEOUT continually
re-triggers).
Ben Skeggs [Mon, 16 Jan 2017 00:36:00 +0000 (10:36 +1000)]
drm/nouveau/fifo/gk104-: better detection of chid when parsing engine status
The previous commit simply changes the interface, but should result in
the same behaviour as previously. This commit has been split out from
it as it can result in a different channel being selected.
Ben Skeggs [Sat, 5 Nov 2016 03:05:14 +0000 (13:05 +1000)]
drm/nouveau/fifo/gf100-: provide notification to user if channel is killed
There are instances (such as non-recoverable GPU page faults) where
NVKM decides that a channel's context is no longer viable, and will
be removed from the runlist.
This commit notifies the owner of the channel when this happens, so
it has the opportunity to take some kind of recovery action instead
of hanging.
Martin Peres [Wed, 18 Jan 2017 21:49:21 +0000 (23:49 +0200)]
drm/nouveau/drm/nouveau/led: prevent a possible use-after-free
If the led class registration fails, we free drm->led but do not reset
it to NULL, which means that the suspend/resume/fini function will act
as if everything went well in init() and will likely crash the kernel.
This patch adds the missing drm->led = NULL.
Reported-by: Emmanuel Pescosta <emmanuelpescosta099@gmail.com> Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Sat, 3 Oct 2015 07:34:25 +0000 (17:34 +1000)]
drm/nouveau/core/mm: replace region list with next pointer
We never have any need for a double-linked list here, and as there's
generally a large number of these objects, replace it with a single-
linked list in order to save some memory.
Ben Skeggs [Sun, 22 May 2016 10:35:16 +0000 (20:35 +1000)]
drm/nouveau/core/client: allow creation of subclients
We want a supervisor client of NVKM (such as the DRM) to be able to
allow sharing of resources (such as memory objects) between clients.
To allow this, the supervisor creates all its clients as children of
itself, and will use an upcoming ioctl to permit sharing.
Currently it's not possible for indirect clients to use subclients.
Supporting this will require an additional field in the main ioctl.
This isn't important currently, but will need to be fixed for virt.
Ben Skeggs [Wed, 25 May 2016 07:33:36 +0000 (17:33 +1000)]
drm/nouveau/core/object: pass client directly to ioctl handlers
nvkm_object::client refers to the client that created the object, which,
is currently always the same as the ioctl caller.
Upcoming patches introduce the concept of subclients, where a parent is
able to access the object trees of its children, making the above no
longer true.
When the PMU firmware is present, the falcons it manages need to have
the lazy-bootstrap flag of their WPR header set so the ACR does not boot
them. Add support for this.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/secboot: set default error value in error register
Set a default error value in the mailbox 0 register so we can catch
cases where the secure boot binary fails early without being able to
report anything.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/secboot: abstract LS firmware loading functions
The WPR and LSB headers, used to generate the LS blob, may have a
different layout and sizes depending on the driver version they come
from. Abstract them and confine their use to driver-specific code.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Split the act of building the ACR blob from firmware files from the rest
of the (chip-dependent) secure boot logic. ACR logic is moved into
acr_rxxx.c files, where rxxx corresponds to the compatible release of
the NVIDIA driver. At the moment r352 and r361 are supported since
firmwares have been released for these versions. Some abstractions are
added on top of r352 so r361 can easily be implemented on top of it by
just overriding a few hooks.
This split makes it possible and easy to reuse the same ACR version on
different chips. It also hopefully makes the code much more readable as
the different secure boot logics are separated. As more chips and
firmware versions will be supported, this is a necessity to not get lost
in code that is already quite complex.
This is a big commit, but it essentially moves things around (and split
the nvkm_secboot structure into two, nvkm_secboot and nvkm_acr). Code
semantics should not be affected.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/secboot: generate HS BL descriptor in hook
Use the HS hook to completely generate the HS BL descriptor, similarly
to what is done in the LS hook, instead of (arbitrarily) using the
acr_v1 format as an intermediate.
This allows us to make the bootloader descriptor structures private to
each implementation, resulting in a cleaner an more consistent design.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Secure firmwares provided by NVIDIA will follow the same overall
principle, but may slightly differ in format, or not use the same
bootloader descriptor even on the same chip. In order to handle
this as gracefully as possible, turn the LS firmware functions into
hooks that can be overloaded as needed.
The current hooks cover the external firmware loading as well as the
bootloader descriptor generation.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This hook can be removed if the function writing the HS
descriptor is aware of WPR settings. Let's do that as it allows us to
make the ACR descriptor structure private and save some code.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
gf100_gr_init_ctxctl() is basically two different functions (one for
use of internal firmware, the other for use of external firmware), but
its current layout makes it look more complex than it is. Split it to
better reflect that fact.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Use the falcon library functions in secure boot. This removes a lot of
code and makes the secure boot flow easier to understand as no register
is directly accessed.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Add a dummy PMU device so the PMU falcon is instanciated and can be used
by secure boot.
We could reuse gk20a's implementation here, but it would fight with
secboot over PMU falcon's ownership and secboot will reset the PMU,
preventing it from operating afterwards. Proper handout between secboot
and pmu is coming along with the actual gm20b PMU implementation, so
use this as a temporary solution.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Falcon processors are used in various places of GPU chips. Although there
exist different versions of the falcon, and some variants exist, the
base set of actions performed on them is the same, which results in lots
of duplicated code.
This patch consolidates the current nvkm_falcon structure and extends it
with the following features:
* Ability for an engine to obtain and later release a given falcon,
* Abstractions for basic operations (IMEM/DMEM access, start, etc)
* Abstractions for secure operations if a falcon is secure
Abstractions make it easy to e.g. start a falcon, without having to care
about its details. For instance, falcons in secure mode need to be
started by writing to a different register.
Right now the abstractions variants only cover secure vs. non-secure
falcon, but more will come as e.g. SEC2 support is added.
This is still a WIP as other functions previously done by
engine/falcon.c need to be reimplemented. However this first step allows
to keep things simple and to discuss basic design.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
projects / kernel.git / log