Andre Przywara [Fri, 3 Mar 2023 10:30:06 +0000 (10:30 +0000)]
refactor(amu): use new AMU feature check routines
The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h), which get updated to cover the v1p1 variant as well.
Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 21 Mar 2023 13:53:19 +0000 (13:53 +0000)]
refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1
So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system
register handling. The latter needs some alignment with the new feature
scheme, but it conceptually overlaps with the ENABLE_AMU option.
Since there is no real need for two separate options, unify both into a
new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at
this point, a subsequent patch will make use of the new feature handling
scheme.
Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Manish Pandey [Mon, 27 Mar 2023 11:08:26 +0000 (13:08 +0200)]
Merge changes from topic "feat_state_part4" into integration
* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SB to new feature handling
refactor(cpufeat): use alternative encoding for "SB" barrier
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
fix(cpufeat): make stub enable functions "static inline"
fix(mpam): feat_detect: support major/minor
Varun Wadekar [Wed, 8 Mar 2023 16:47:38 +0000 (16:47 +0000)]
fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4
The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions
are received simultaneously from different sources. This hardware issue
impacts NVIDIA server platforms that use more than two T241 chips
interconnected. Each chip has support for 320 {E}SPIs.
This issue occurs when multiple packets from different GICs are
incorrectly interleaved at the target chip. The erratum text below
specifies exactly what can cause multiple transfer packets susceptible
to interleaving and GIC state corruption. GIC state corruption can
lead to a range of problems, including kernel panics, and unexpected
behavior.
The workaround is to ensure that MMIO accesses target the GIC on the
socket that holds the data, for example SPI ranges owned by the socket’s
GIC. This ensures that the GIC will not utilize the inter-socket AXI
Stream interface for servicing these GIC MMIO accesses.
This patch updates the functions that use the GICD_In{E} registers to
ensure that the accesses are directed to the chip that owns the SPI,
instead of using the global alias.
Andre Przywara [Thu, 23 Mar 2023 11:43:22 +0000 (11:43 +0000)]
fix(fpga): include missing header file
Since transitioning over FEAT_SPE to the new feature checking scheme, we
make use of the new is_feat_spe_supported() function in the Arm FPGA
platform code. However this missed to include the header file, so the
build broke.
Add the arch_features.h header to make arm_fpga compile again.
Change-Id: I5c8feecfcc6fb5845a6671842850df1943086a58 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
fix(versal-net): use spin_lock instead of bakery_lock
In ARM v8.2 the cache will turn off automatically when cpu power down.
Therefore use the spin_lock instead of bakery_lock for the platform in
which HW_ASSISTED_COHERENCY is enabled.
In Versal NET platform HW_ASSISTED_COHERENCY is enabled so it will use
spin lock. In ZynqMP and Versal HW_ASSISTED_COHERENCY is not enabled so
it will use bakery_lock.
Also remove bakery_lock_init() because it is empty.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I18ff939b51f16d7d3484d8564d6ee6c586f363d8
Jay Buddhabhatti [Thu, 23 Mar 2023 05:44:16 +0000 (22:44 -0700)]
fix(versal-net): correct aff level for cpu off
CPU suspend is calling validate_power_state PSCI opps which returns
power domain state for CPU suspend according to PSTATE type. In case of
power down it assigns PLAT_MAX_OFF_STATE to all affinity level which is
incorrect since for CPU suspend we need to set only MPIDR_AFFLVL0 which
is CPU state. So correct affinity level for CPU suspend.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I39f92790ea74e4cab8e87342e73e1ac211a46fcd
refactor(fvp): use RSS API to retrieve attestation token and key
Retrieved the platform attestation token and delegated realm attestation
key through the PSA delegated attestation layer.
Even though FVP doesn't support RSS hardware today, it can still
leverage the RSS implementation of these PSA interfaces in their mocking
form (see PLAT_RSS_NOT_SUPPORTED).
Therefore, platform APIs now call these PSA interfaces instead of
directly providing these hardcoded values.
Change-Id: I31d0ca58f6f1a444f513d954da4e3e67757321ad Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Andre Przywara [Wed, 22 Feb 2023 17:55:59 +0000 (17:55 +0000)]
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
At the moment we only support for FEAT_RNG to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (FEAT_RNG=2), by splitting
is_armv8_5_rng_present() into an ID register reading function and a second
function to report the support status. That function considers both build
time settings and runtime information (if needed), and is used before we
access the RNDRRS system register.
Change the QEMU platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I1a4a538d5ad395fead7324f297d0056bda4f84cb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 22 Feb 2023 16:53:50 +0000 (16:53 +0000)]
refactor(cpufeat): align FEAT_SEL2 to new feature handling
In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
align its handling with the other CPU features.
Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 27 Jan 2023 14:09:20 +0000 (14:09 +0000)]
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
At the moment we only support for FEAT_NV2 to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (CTX_INCLUDE_NEVE_REGS=2), by
splitting get_armv8_4_feat_nv_support() into an ID register reading
function and a second function to report the support status. That
function considers both build time settings and runtime information
(if needed), and is used before we access the VNCR_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_nv2_supported() function to guard its execution.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I85b080641995fb72cfd4ac933f7a3f75770c2cb9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 27 Jan 2023 12:25:49 +0000 (12:25 +0000)]
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
At the moment we only support FEAT_TWED to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_TWED=2), by splitting
is_armv8_6_twed_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we set the trap delay time.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I58626230ef0af49886c0a197abace01e81f661d2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 17 Nov 2022 17:30:43 +0000 (17:30 +0000)]
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
At the moment we only support FEAT_CSV2_2 to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting
is_armv8_0_feat_csv2_2_present() into an ID register reading function
and a second function to report the support status. That function
considers both build time settings and runtime information (if needed),
and is used before we access the SCXTNUM_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_csv2_2_supported() function to guard its execution.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 17 Nov 2022 17:30:43 +0000 (17:30 +0000)]
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
At the moment we only support FEAT_ECV to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting
is_feat_ecv_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access the CNTPOFF_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_ecv_supported() function to guard its execution.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 26 Jan 2023 15:27:38 +0000 (15:27 +0000)]
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
At the moment we only support FEAT_PAN to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_PAN=2), by splitting
is_armv8_1_pan_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we PAN specific setup.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I58e5fe8d3c9332820391c7d93a8fb9dba4cf754a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 17 Nov 2022 16:42:09 +0000 (16:42 +0000)]
refactor(cpufeat): align FEAT_SB to new feature handling
FEAT_SB introduces a new speculation barrier instruction, that is more
lightweight than a "dsb; isb" combination. We use that in a hot path,
so cannot afford and don't want a runtime detection mechanism.
Nevertheless align the implementation of the feature detection part
with the other features, but renaming the detection function, and
updating the FEAT_DETECTION code. Also update the documentation.
Change-Id: I2b86dfd1ad259c3bb99ab5186e2911ace454b54c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 25 Nov 2022 14:10:13 +0000 (14:10 +0000)]
refactor(cpufeat): use alternative encoding for "SB" barrier
The "sb" barrier instruction is a rather new addition to the AArch64
instruction set, so it is not recognised by all toolchains. On top of
that, the GNU assembler denies this instruction, unless a compatible
processor is selected:
asm_macros.S:223: Error: selected processor does not support `sb'
Provide an alternative encoding of the "sb" instruction, by using a
system register write, as this is the group where the barrier
instructions borrow their encoding space from.
This results in the exact same opcode to be generated, and any
disassembler will decode this instruction as "sb".
Change-Id: I5f44c8321e0cc04c784e02bd838e964602a96a8e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 17 Nov 2022 16:42:09 +0000 (16:42 +0000)]
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
At the moment we only support access to the trace unit by system
registers (SYS_REG_TRACE) to be either unconditionally compiled in, or
to be not supported at all.
Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), by
adding is_feat_sys_reg_trace_supported(). That function considers both
build time settings and runtime information (if needed), and is used
before we access SYS_REG_TRACE related registers.
The FVP platform decided to compile in support unconditionally (=1),
even though this is an optional feature, so it is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.
Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 22 Mar 2023 13:25:00 +0000 (13:25 +0000)]
fix(cpufeat): make stub enable functions "static inline"
For builds where we don't have a certain feature enabled, we provide
empty stub xxx_enable() functions in a header file. This way we
avoid #ifdef's in the code, and can call the enable function
unconditionally. When compiling with -O1 or higher, the compiler will
even optimise out the whole call, so the symbol will never make it into
any object file.
When compiling with optimisations turned off, the function stub will
survive, and could make it into multiple object files, which would lead
to a multiple definitons error.
Avoid this by defining those stub functions as "static inline". The
"static" will avoid the multiple definitions problems, the "inline" will
avoid a potential compiler warning about unused functions.
This patterns is used extensively in the Linux kernel.
Change-Id: Iad07bb946aab372587c83f2423b4983bf3817990 Reported-by: Chris Kay <chris.kay@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 21 Mar 2023 14:44:59 +0000 (14:44 +0000)]
fix(mpam): feat_detect: support major/minor
The MPAM CPU ID version number is split between two CPU ID register
fields, with the second being a fractional field, allowing for instance
for a "MPAM v1.1" number. The read_feat_mpam_version() function merges
those two fields to form a "4.4" fixed point fractional number, but the
limit check in the check_feature() function was not taking this into
account.
To support MPAM major version 1, extend the limit from "1" to "17", to
cover the current maximum version of "MPAM v1.1".
This fixes FVP runs with "has_mpam=1" and FEATURE_DETECTION enabled.
Change-Id: Icb557741d597e4e43eaf658b78f18af6e9fb439e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Bipin Ravi [Mon, 20 Mar 2023 21:21:24 +0000 (22:21 +0100)]
Merge changes from topics "qemu", "qemu_sbsa" into integration
* changes:
feat(qemu): add A76/N1 cpu support for virt
feat(qemu): add "neoverse-n1" cpu support
feat(qemu): make coherent memory section optional
refactor(qemu): make use of setup_page_tables()
Manish Pandey [Mon, 20 Mar 2023 17:25:00 +0000 (18:25 +0100)]
Merge changes from topic "feat_state_part3" into integration
* changes:
refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKED
refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKED
feat(libc): add support for fallthrough statement
refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED
refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS
fix(spe): drop SPE EL2 context switch code
Andre Przywara [Thu, 17 Nov 2022 16:42:09 +0000 (16:42 +0000)]
refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKED
At the moment we only support FEAT_VHE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_VHE=2), by splitting
is_armv8_1_vhe_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we access VHE related registers.
Also move the context saving code from assembly to C, and use the new
is_feat_vhe_supported() function to guard its execution.
Enable VHE in its runtime detection version for all FVP builds.
Change-Id: Ib397cd0c83e8c709bd6fed603560e39901fa672b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 17 Nov 2022 16:42:09 +0000 (16:42 +0000)]
refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKED
At the moment we only support FEAT_MPAM to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_MPAM_FOR_LOWER_ELS=2), by
splitting get_mpam_version() into an ID register reading
function and a second function to report the support status. That
function considers both build time settings and runtime information (if
needed), and is used before we access MPAM related registers.
Also move the context saving code from assembly to C, and use the new
is_feat_mpam_supported() function to guard its execution.
ENABLE_MPAM_FOR_LOWER_ELS defaults to 0, so add a stub enable function
to cover builds with compiler optimisations turned off. The unused
mpam_enable() function call will normally be optimised away (because it
would never be called), but with -O0 the compiler will leave the symbol
in the object file.
Change-Id: I531d87cb855a7c43471f861f625b5a6d4bc61313 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 21 Feb 2023 12:05:29 +0000 (12:05 +0000)]
feat(libc): add support for fallthrough statement
Modern C compilers warn about unannotated switch/case fallthrough code,
and require either a comment with some magic words, or an explicit
compiler attribute.
Since some TF-A static analysis CI check suggests having a "fallthrough;"
statement instead of a comment, introduce a macro that implements that
statement, and emits the proper compiler attribute.
Change-Id: Ib34e615fb48d0f4a340aabfad4472e08d5c70248 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 17 Nov 2022 16:42:09 +0000 (16:42 +0000)]
refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED
At the moment we only support FEAT_SPE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_SPE_FOR_NS=2), by splitting
is_armv8_2_feat_spe_present() into an ID register reading function and
a second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we access SPE related registers.
Previously SPE was enabled unconditionally for all platforms, change
this now to the runtime detection version.
Change-Id: I830c094107ce6a398bf1f4aef7ffcb79d4f36552 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 3 Feb 2023 15:30:14 +0000 (15:30 +0000)]
refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS
At the moment we hardcode the SPE functionality to be available on the
non-secure side only, by setting MDCR_EL2.E2PB accordingly.
This should be reflected in the feature selection symbol, so rename that
to ENABLE_SPE_FOR_NS, to make it clearer that SPE is not supported in
the secure world.
Change-Id: I3f9b48eab1a45d6ccfcbb9c90a11eeb66867ad9a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 3 Feb 2023 15:23:59 +0000 (15:23 +0000)]
fix(spe): drop SPE EL2 context switch code
At the moment we hardcode the SPE functionality to be available on the
non-secure side only, by setting MDCR_EL3.NSPB accordingly.
This also means that the secure world cannot use SPE, so there is no
need to context switch the PMSCR_EL2 register.
Drop the SPE bits from the EL2 context switch code. If any of the other
EL2 worlds wish to start using SPE, this can be brought back.
Change-Id: Ie0fedb2aeb722a2c9db316051fbbe57ca0e3c0c9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
As per SMCCC spec Table 2.1 bit 23:17 must be zero (MBZ),
for all Fast Calls, when bit[31] == 1.
Adding this check to ensure SMC FIDs when get to the SMC handler
have these bits (23:17) cleared, if not capture and report them
as an unknown SMCs at the core.
Also the C runtime stack is copied to the stackpointer well in
advance, to leverage the existing el3_exit routine for unknown SMC.
Mark Brown [Tue, 14 Mar 2023 20:13:03 +0000 (20:13 +0000)]
feat(tcr2): support FEAT_TCR2
Arm v8.9 introduces FEAT_TCR2, adding extended translation control
registers. Support this, context switching TCR2_EL2 and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option so
the right decision can be made by the code at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I297452acd8646d58bac64fc15e05b06a543e5148
Boyan Karatotev [Thu, 17 Nov 2022 12:01:29 +0000 (12:01 +0000)]
refactor(cpus): shorten errata flag defines
The cpu-ops makefile has errata flag definition and flag processing done
per flag in separate parts in the file. Rework this to make a list and
do this in a much more concise way.
To ensure no flags were missed, a bash script [1] was used to verify all
errata flags made it across. Only the first few flags with different
naming were checked manually.
Maksims Svecovs [Wed, 15 Mar 2023 13:24:44 +0000 (13:24 +0000)]
style(hooks): adds Arm copyright style fix
Adds a check to pre-commit hook that makes sure "Arm" is written in a
correct case and not "arm" or "ARM". Same as a copyright-year check, the
hook will fix the issue and prompt user to stage the fix.
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).
BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.
feat(morello): implement methods to retrieve soc-id information
Added silicon revision in the platform information SDS structure.
Implemented platform functions to retrieve the soc-id information
for the morello SoC platform. SoC revision, which is same as
silicon revision, is fetched from the morello_plat_info structure
and SoC version is populated with the part number from SSC_VERSION
register, and is reflected in bits[0:15] of soc-id.
Marco Felsch [Wed, 9 Nov 2022 11:59:09 +0000 (12:59 +0100)]
feat(build): add support for new binutils versions
Users of GNU ld (BPF) from binutils 2.39+ will observe multiple instaces
of a new warning when linking the bl*.elf in the form:
ld.bfd: warning: stm32mp1_helper.o: missing .note.GNU-stack section implies executable stack
ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker
ld.bfd: warning: bl2.elf has a LOAD segment with RWX permissions
ld.bfd: warning: bl32.elf has a LOAD segment with RWX permissions
Fix it in a similar way to what the Linux kernel does, see:
https://lore.kernel.org/all/20220810222442.2296651-1-ndesaulniers@google.com/
Following the reasoning there, we set "-z noexecstack" for all linkers
(although LLVM's LLD defaults to it) and optional add
--no-warn-rwx-segments since this a ld.bfd related.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Change-Id: I9430f5fa5036ca88da46cd3b945754d62616b617
Marco Felsch [Thu, 24 Nov 2022 10:02:05 +0000 (11:02 +0100)]
build(makefile): add helper to detect linker options
This is a small helper to check for possible linker options. If the
linker supports the requested option it is returned and if not nothing
will be returned, e.g.:
Merge changes from topic "imx8m_misc_changes" into integration
* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m
projects / arm-tf.git / log