Stephen Boyd [Mon, 1 Jun 2020 20:00:28 +0000 (13:00 -0700)]
Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-silabs' into clk-next
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for Qualcomm's MSM8939 Generic Clock Controller
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
* clk-mmp:
clk: mmp2: Add audio clock controller driver
dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding
clk: mmp2: Add support for power islands
dt-bindings: marvell,mmp2: Add ids for the power domains
dt-bindings: clock: Make marvell,mmp2-clock a power controller
clk: mmp2: Add the audio clock
clk: mmp2: Add the I2S clocks
clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()
clk: mmp2: Move thermal register defines up a bit
dt-bindings: marvell,mmp2: Add clock id for the Audio clock
dt-bindings: marvell,mmp2: Add clock id for the I2S clocks
clk: mmp: frac: Allow setting bits other than the numerator/denominator
clk: mmp: frac: Do not lose last 4 digits of precision
* clk-intel:
clk: intel: remove redundant initialization of variable rate64
clk: intel: Add CGU clock driver for a new SoC
dt-bindings: clk: intel: Add bindings document & header file for CGU
* clk-ingenic:
clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused
clk: X1000: Add FIXDIV for SSI clock of X1000.
dt-bindings: clock: Add and reorder ABI for X1000.
clk: Ingenic: Add CGU driver for X1830.
dt-bindings: clock: Add X1830 clock bindings.
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
clk: Ingenic: Remove unnecessary spinlock when reading registers.
* clk-qcom:
clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
clk: qcom: gcc: Add support for Secure control source clock
dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
clk: qcom: gcc: Add support for a new frequency for SC7180
clk: qcom: Add DT bindings for MSM8939 GCC
clk: qcom: gcc: Add missing UFS clocks for SM8150
clk: qcom: gcc: Add GPU and NPU clocks for SM8150
clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc
clk: qcom: gdsc: Handle GDSC regulator supplies
clk: qcom: msm8916: Fix the address location of pll->config_reg
* clk-silabs:
clk: clk-si5341: Add support for the Si5345 series
Stephen Boyd [Mon, 1 Jun 2020 20:00:21 +0000 (13:00 -0700)]
Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2600' into clk-next
* clk-unisoc:
clk: sprd: add mipi_csi_xx gate clocks
clk: sprd: add dt-bindings include for mipi_csi_xx clocks
dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A
clk: sprd: check its parent status before reading gate clock
clk: sprd: return correct type of value for _sprd_pll_recalc_rate
clk: sprd: mark the local clock symbols static
* clk-trivial:
clk: versatile: remove redundant assignment to pointer clk
clk: clk-xgene: Fix a typo in Kconfig
clk: Remove unused inline function clk_debug_reparent
* clk-bcm:
clk: bcm2835: Constify struct debugfs_reg32
clk: bcm2835: Remove casting to bcm2835_clk_register
clk: bcm2835: Fix return type of bcm2835_register_gate
Stephen Boyd [Mon, 1 Jun 2020 20:00:00 +0000 (13:00 -0700)]
Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' and 'clk-ti' into clk-next
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- Support for Intel Agilex clks
* clk-tegra:
clk: tegra: Add Tegra210 CSI TPG clock gate
clk: tegra30: Use custom CCLK implementation
clk: tegra20: Use custom CCLK implementation
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: Add custom CCLK implementation
clk: tegra: Remove the old emc_mux clock for Tegra210
clk: tegra: Implement Tegra210 EMC clock
clk: tegra: Export functions for EMC clock scaling
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
clk: tegra: Rename Tegra124 EMC clock source file
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
* clk-imx:
clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
clk: imx: add imx8m_clk_hw_composite_bus
clk: imx: add mux ops for i.MX8M composite clk
clk: imx8m: migrate A53 clk root to use composite core
clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
clk: imx8mp: Define gates for pll1/2 fixed dividers
clk: imx: imx8mp: fix pll mux bit
clk: imx8m: drop clk_hw_set_parent for A53
dt-bindings: clocks: imx8mp: Add ids for audiomix clocks
clk: imx: Add helpers for passing the device as argument
clk: imx: pll14xx: Add the device as argument when registering
clk: imx: gate2: Allow single bit gating clock
clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait
clk: imx: clk-sscg-pll: Remove unnecessary blank lines
clk: imx: drop the dependency on ARM64 for i.MX8M
clk: imx7ulp: make it easy to change ARM core clk
clk: imx: imx6ul: change flexcan clock to support CiA bitrates
* clk-zynq:
clk: zynqmp: Make zynqmp_clk_get_max_divisor static
clk: zynqmp: Update fraction clock check from custom type flags
clk: zynqmp: Add support for custom type flags
clk: zynqmp: fix memory leak in zynqmp_register_clocks
clk: zynqmp: Fix invalid clock name queries
clk: zynqmp: Fix divider2 calculation
clk: zynqmp: Limit bestdiv with maxdiv
* clk-socfpga:
clk: socfpga: agilex: add clock driver for the Agilex platform
dt-bindings: documentation: add clock bindings information for Agilex
clk: socfpga: add const to _ops data structures
clk: socfpga: remove clk_ops enable/disable methods
clk: socfpga: stratix10: use new parent data scheme
* clk-at91:
clk: at91: allow setting all PMC clock parents via DT
clk: at91: allow setting PCKx parent via DT
clk: at91: optimize pmc data allocation
clk: at91: pmc: decrement node's refcount
clk: at91: pmc: do not continue if compatible not located
clk: at91: Add peripheral clock for PTC
* clk-ti:
clk: ti: dra7: remove two unused symbols
clk: ti: dra7xx: fix RNG clock parent
clk: ti: dra7xx: mark MCAN clock as DRA76x only
clk: ti: dra7xx: fix gpu clkctrl parent
clk: ti: omap5: Add proper parent clocks for l4-secure clocks
clk: ti: omap4: Add proper parent clocks for l4-secure clocks
clk: ti: composite: fix memory leak
Stephen Boyd [Mon, 1 Jun 2020 19:59:46 +0000 (12:59 -0700)]
Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next
- Allow the COMMON_CLK config to be selectable
* clk-selectable:
clk: Move HAVE_CLK config out of architecture layer
MIPS: Loongson64: Drop asm/clock.h include
ARM: mmp: Remove legacy clk code
clk: Allow the common clk framework to be selectable
mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
MIPS: Remove redundant CLKDEV_LOOKUP selects
h8300: Remove redundant CLKDEV_LOOKUP selects
arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
ARM: Remove redundant CLKDEV_LOOKUP selects
ARM: Remove redundant COMMON_CLK selects
* clk-amlogic:
clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
clk: meson: meson8b: Fix the polarity of the RESET_N lines
clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
clk: meson: g12a: Prepare the GPU clock tree to change at runtime
clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
clk: meson: meson8b: make the hdmi_sys clock tree mutable
clk: meson8b: export the HDMI system clock
* clk-renesas:
dt-bindings: clock: renesas: mstp: Convert to json-schema
dt-bindings: clock: renesas: div6: Convert to json-schema
clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
clk: renesas: cpg-mssr: Add R8A7742 support
dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
clk: renesas: Add r8a7742 CPG Core Clock Definitions
dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
MAINTAINERS: Add DT Bindings for Renesas Clock Generators
clk: renesas: r9a06g032: Fix some typo in comments
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
* clk-samsung:
clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
* clk-allwinner:
clk: sunxi: Fix incorrect usage of round_down()
Nearly each Baikal-T1 IP-core is supposed to have a clock source
of particular frequency. But since there are greater than five
IP-blocks embedded into the SoC, the CCU PLLs can't fulfill all the
needs. Baikal-T1 CCU provides a set of fixed and configurable clock
dividers in order to generate a necessary signal for each chip
sub-block.
This driver creates the of-based hardware clocks for each divider
available in Baikal-T1 CCU. The same way as for PLLs we split the
functionality up into the clocks operations (gate, ungate, set rate,
etc) and hardware clocks declaration/registration procedures.
In accordance with the CCU documentation all its dividers are distributed
into two CCU sub-blocks: AXI-bus and system devices reference clocks.
The former sub-block is used to supply the clocks for AXI-bus interfaces
(AXI clock domains) and the later one provides the SoC IP-cores reference
clocks. Each sub-block is represented by a dedicated DT node, so they
have different compatible strings to distinguish one from another.
For some reason CCU provides the dividers of different types. Some
dividers can be gateable some can't, some are fixed while the others
are variable, some have special divider' limitations, some've got a
non-standard register layout and so on. In order to cover all of these
cases the hardware clocks driver is designed with an info-descriptor
pattern. So there are special static descriptors declared for the
dividers of each type with additional flags describing the block
peculiarity. These descriptors are then used to create hardware clocks
with proper operations.
Some CCU dividers provide a way to reset a domain they generate
a clock for. So the CCU AXI-bus and CCU system devices clock
drivers also perform the reset controller registration.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-5-Sergey.Semin@baikalelectronics.ru
[sboyd@kernel.org: Drop return from void function, silence sparse
warnings about initializing structs with NULL vs. integer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Baikal-T1 is supposed to be supplied with a high-frequency external
oscillator. But in order to create signals suitable for each IP-block
embedded into the SoC the oscillator output is primarily connected to
a set of CCU PLLs. There are five of them to create clocks for the MIPS
P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains.
The last three domains though named by the biggest system interfaces in
fact include nearly all of the rest SoC peripherals. Each of the PLLs is
based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper
(so called safe PLL' clocks switcher) to simplify the PLL configuration
procedure.
This driver creates the of-based hardware clocks to use them then in
the corresponding subsystems. In order to simplify the driver code we
split the functionality up into the PLLs clocks operations and hardware
clocks declaration/registration procedures.
Even though the PLLs are based on the same IP-core, they may have some
differences. In particular, some CCU PLLs support the output clock change
without gating them (like CPU or PCIe PLLs), while the others don't, some
CCU PLLs are critical and aren't supposed to be gated. In order to cover
all of these cases the hardware clocks driver is designed with an
info-descriptor pattern. So there are special static descriptors declared
for each PLL, which is then used to create a hardware clock with proper
operations. Additionally debugfs-files are provided for each PLL' field
to make sure the implemented rate-PLLs-dividers calculation algorithm is
correct.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-4-Sergey.Semin@baikalelectronics.ru
[sboyd@kernel.org: Silence sparse warning about initializing structs
with NULL vs. integer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
After being gained by the CCU PLLs the signals must be transformed to
be suitable for the clock-consumers. This is done by a set of dividers
embedded into the CCU. A first block of dividers is used to create
reference clocks for AXI-bus of high-speed peripheral IP-cores of the
chip. The second block dividers alter the PLLs output signals to be then
consumed by SoC peripheral devices. Both block DT nodes are ordinary
clock-providers with standard set of properties supported. But in addition
to that each clock provider can be used to reset the corresponding clock
domain. This makes the AXI-bus and System Devices CCU DT nodes to be also
reset-providers.
Baikal-T1 Clocks Control Unit is responsible for transformation of a
signal coming from an external oscillator into clocks of various
frequencies to propagate them then to the corresponding clocks
consumers (either individual IP-blocks or clock domains). In order
to create a set of high-frequency clocks the external signal is
firstly handled by the embedded into CCU PLLs. So the corresponding
dts-node is just a normal clock-provider node with standard set of
properties. Note as being part of the Baikal-T1 System Controller its
DT node is supposed to be a child the system controller node.
Weiyi Lu [Wed, 27 May 2020 06:25:49 +0000 (14:25 +0800)]
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
When some new clock supports are introduced, e.g. [1]
it might lead to an error although it should be NULL because
clk_init_data is on the stack and it might have random values
if using without initialization.
Add the missing initial value to clk_init_data.
Mike Looijmans [Thu, 7 May 2020 06:15:44 +0000 (08:15 +0200)]
clk: clk-si5341: Add support for the Si5345 series
Add support for the Si5342, Si5344 and Si5345 chips. These are equivalent
to the Si5341 family, but with more clock input options (which are not
supported yet by this driver).
Stephen Boyd [Thu, 28 May 2020 23:38:37 +0000 (16:38 -0700)]
clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused
This device id table is passed to of_match_node() later on in probe, but
on CONFIG_OF=n builds of_match_node() doesn't do anything with the
arguments. Lets just mark the table unused so that the compiler doesn't
complain about this.
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
directly derived from the output of SSIPLL, but from the clock
obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
is added for this purpose, and ensure that it initialized before
"X1000_CLK_SSIMUX" when initializing the clocks.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU, and gates of CPU, PCLK
are also added.
3.Use "CLK_OF_DECLARE_DRIVER" like the other CGU drivers.
dt-bindings: clock: Add and reorder ABI for X1000.
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
directly derived from the output of SSIPLL, but from the clock
obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
is added for this purpose, it must between "X1000_CLK_SSIPLL"
and "X1000_CLK_SSIMUX", otherwise an error will occurs when
initializing the clock. These ABIs are only used for X1000, and
I'm sure that no other devicetree out there is using these ABIs,
so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added.
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
The PLL of X1830 Soc from Ingenic has been greatly changed,
the bypass control is placed in another register, so now two
registers may needed to control the PLL. To this end, a new
"bypass_reg" was introduced. In addition, when calculating
rate, the PLL of X1830 introduced an extra 2x multiplier,
so a new "rate_multiplier" was introduced. And adjust the
code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.
Colin Ian King [Thu, 28 May 2020 22:12:19 +0000 (23:12 +0100)]
clk: intel: remove redundant initialization of variable rate64
The variable rate64 is being initialized with a value that is never read
and it is being updated later with a new value. The initialization is
redundant and can be removed.
Lubomir Rintel [Tue, 19 May 2020 22:41:51 +0000 (00:41 +0200)]
clk: mmp2: Add audio clock controller driver
This is a driver for a block that generates master and bit clocks for
the I2S interface. It's separate from the PMUs that generate clocks for
the peripherals.
Lubomir Rintel [Tue, 19 May 2020 22:41:49 +0000 (00:41 +0200)]
clk: mmp2: Add support for power islands
Apart from the clocks and resets, the PMU hardware also controls power
to peripherals that are on separate power islands. On MMP2, that's the
GC860 GPU and the SSPA audio interface, while on MMP3 also the camera
interface is on a separate island, along with the pair of GC2000 and GC300
GPUs and the SSPA.
Lubomir Rintel [Tue, 19 May 2020 22:41:39 +0000 (00:41 +0200)]
clk: mmp: frac: Do not lose last 4 digits of precision
While calculating the output rate of a fractional divider clock, the
value is divided and multipled by 10000, discarding the least
significant digits -- presumably to fit the intermediate value within 32
bits.
The precision we're losing is, however, not insignificant for things like
I2S clock. Maybe also elsewhere, now that since commit a44dec6c5efc ("clk:
mmp2: Stop pretending PLL outputs are constant") the parent rates are more
precise and no longer rounded to 10000s.
Eddie James [Wed, 8 Apr 2020 20:36:16 +0000 (15:36 -0500)]
clk: ast2600: Fix AHB clock divider for A1
The latest specs for the AST2600 A1 chip include some different bit
definitions for calculating the AHB clock divider. Implement these in
order to get the correct AHB clock value in Linux.
Chunyan Zhang [Wed, 27 May 2020 05:36:35 +0000 (13:36 +0800)]
clk: sprd: check its parent status before reading gate clock
Some clocks only can be accessed if their parent is enabled. mipi_csi_xx
clocks on SC9863A are an examples. We have to ensure the parent clock is
enabled when reading those clocks.
Colin Ian King [Tue, 26 May 2020 22:41:16 +0000 (23:41 +0100)]
clk: versatile: remove redundant assignment to pointer clk
The pointer clk is being initialized with a value that is never read
and is being updated with a new value later on. The initialization
is redundant and can be removed.
Jason Yan [Fri, 17 Apr 2020 07:35:23 +0000 (15:35 +0800)]
clk: ti: dra7: remove two unused symbols
Fix the following gcc warning:
drivers/clk/ti/clk-7xx.c:320:43: warning: ‘dra7_gpu_sys_clk_data’
defined but not used [-Wunused-const-variable=]
static const struct omap_clkctrl_div_data dra7_gpu_sys_clk_data
__initconst = {
^~~~~~~~~~~~~~~~~~~~~
drivers/clk/ti/clk-7xx.c:315:27: warning: ‘dra7_gpu_sys_clk_parents’
defined but not used [-Wunused-const-variable=]
static const char * const dra7_gpu_sys_clk_parents[] __initconst = {
^~~~~~~~~~~~~~~~~~~~~~~~
Michał Mirosław [Mon, 4 May 2020 22:37:57 +0000 (00:37 +0200)]
clk: at91: allow setting all PMC clock parents via DT
We need to have clocks accessible via phandle to select them
as peripheral clock parent using assigned-clock-parents in DT.
Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available.
Chunyan Zhang [Tue, 19 May 2020 03:00:36 +0000 (11:00 +0800)]
clk: sprd: return correct type of value for _sprd_pll_recalc_rate
The function _sprd_pll_recalc_rate() defines return value to unsigned
long, but it would return a negative value when malloc fail, changing
to return its parent_rate makes more sense, since if the callback
.recalc_rate() is not set, the framework returns the parent_rate as
well.
Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC named Lightning Mountain(LGM). It provides
programming interfaces to control & configure all CPU & peripheral clocks.
Add common clock framework based clock controller driver for CGU.
This patch adds support for the MSM8939 GCC. The MSM8939 is based on the
MSM8916. MSM8939 is compatible in several ways with MSM8916 but, has
additional functional blocks added which require additional PLL sources. In
some cases functional blocks from the MSM8916 have different clock sources
or different supported frequencies.
Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Co-developed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lkml.kernel.org/r/20200517131348.688405-3-bryan.odonoghue@linaro.org Tested-by: Konrad Dybcio <konradybcio@gmail.com>
[sboyd@kernel.org: Drop ret in probe function to remove unused
variable] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Tue, 12 May 2020 18:16:46 +0000 (13:16 -0500)]
dt-bindings: documentation: add clock bindings information for Agilex
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Clock generation unit(CGU) is a clock controller IP of Intel's Lightning
Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock
controller driver of LGM.
Tejas Patel [Thu, 12 Mar 2020 21:31:39 +0000 (14:31 -0700)]
clk: zynqmp: Update fraction clock check from custom type flags
Older firmware version sets BIT(13) in clkflag to mark a
divider as fractional divider. Updated firmware version sets BIT(4)
in type flags to mark a divider as fractional divider since
BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk
framework flags.
To support both old and new firmware version, consider BIT(13) from
clkflag and BIT(4) from type_flag to check if divider is fractional
or not.
To maintain compatibility BIT(13) of clkflag in firmware will not be
used in future for any purpose and will be marked as unused.
Rajan Vaja [Mon, 2 Mar 2020 21:50:42 +0000 (13:50 -0800)]
clk: zynqmp: Fix invalid clock name queries
The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling zynqmp_pm_clock_get_name() in versal_get_clock_info() function.
Tejas Patel [Mon, 2 Mar 2020 21:50:41 +0000 (13:50 -0800)]
clk: zynqmp: Fix divider2 calculation
zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock,
considering best possible combination of DIV1 and DIV2.
To find best possible values of DIV1 and DIV2, DIV1's parent rate
should be consider and not DIV2's parent rate since it would rate of
div1 clock. Consider a below topology,
out_clk->div2_clk->div1_clk->fixed_parent
where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock
of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk.
Existing code divides parent rate of div2_clk's clock instead of
div1_clk's parent rate, which is wrong.
Fix the same by considering div1's parent clock rate.
These callbacks are cast to bcm2835_clk_register so that there is no
error about incompatible pointer types. Unfortunately, this is a control
flow integrity violation, which verifies that the callback function's
types match the prototypes exactly before jumping.
To fix this, change the second parameter of all functions void * and use
a local variable with the correct type so that everything works
properly. With this, the only use of bcm2835_clk_register is in struct
bcm2835_clk_desc so we can just remove it and use the type directly.
clk: bcm2835: Fix return type of bcm2835_register_gate
bcm2835_register_gate is used as a callback for the clk_register member
of bcm2835_clk_desc, which expects a struct clk_hw * return type but
bcm2835_register_gate returns a struct clk *.
This discrepancy is hidden by the fact that bcm2835_register_gate is
cast to the typedef bcm2835_clk_register by the _REGISTER macro. This
turns out to be a control flow integrity violation, which is how this
was noticed.
Change the return type of bcm2835_register_gate to be struct clk_hw *
and use clk_hw_register_gate to do so. This should be a non-functional
change as clk_register_gate calls clk_hw_register_gate anyways but this
is needed to avoid issues with further changes.
Stephen Boyd [Tue, 26 May 2020 22:00:43 +0000 (15:00 -0700)]
Merge tag 'clk-imx-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clk driver updates from Shawn Guo:
- A few patches from Abel Vesa as preparation of adding audiomix clock
support
- A couple of cleanups from Anson Huang on clk-sscg-pll and clk-pllv3
driver
- Update imx7ulp clock driver to use imx_clk_hw_cpu() for making the
change of ARM core clock easier
- Drop dependency on ARM64 for i.MX8M clock driver, as there is a move
to support aarch32 mode on aarch64 hardware
- A series from Peng Fan to improve i.MX8M clock drivers, using
composite clock for core and bus clk slice
- Set a better parent clock for flexcan on i.MX6UL to support CiA102
defined bit rates
* tag 'clk-imx-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
clk: imx: add imx8m_clk_hw_composite_bus
clk: imx: add mux ops for i.MX8M composite clk
clk: imx8m: migrate A53 clk root to use composite core
clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
clk: imx8mp: Define gates for pll1/2 fixed dividers
clk: imx: imx8mp: fix pll mux bit
clk: imx8m: drop clk_hw_set_parent for A53
dt-bindings: clocks: imx8mp: Add ids for audiomix clocks
clk: imx: Add helpers for passing the device as argument
clk: imx: pll14xx: Add the device as argument when registering
clk: imx: gate2: Allow single bit gating clock
clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait
clk: imx: clk-sscg-pll: Remove unnecessary blank lines
clk: imx: drop the dependency on ARM64 for i.MX8M
clk: imx7ulp: make it easy to change ARM core clk
clk: imx: imx6ul: change flexcan clock to support CiA bitrates
Stephen Boyd [Thu, 21 May 2020 22:52:41 +0000 (15:52 -0700)]
Merge tag 'for-5.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra
Pull Tegra clk driver updates from Thierry Reding:
These are a couple of changes to implement EMC frequency scaling on
Tegra210, CPU frequency scaling on Tegra20 and Tegra30 as well as a
special clock gate for the CSI test pattern generator on Tegra210.
* tag 'for-5.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Add Tegra210 CSI TPG clock gate
clk: tegra30: Use custom CCLK implementation
clk: tegra20: Use custom CCLK implementation
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: Add custom CCLK implementation
clk: tegra: Remove the old emc_mux clock for Tegra210
clk: tegra: Implement Tegra210 EMC clock
clk: tegra: Export functions for EMC clock scaling
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
clk: tegra: Rename Tegra124 EMC clock source file
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Stephen Boyd [Thu, 21 May 2020 22:43:32 +0000 (15:43 -0700)]
Merge tag 'clk-v5.8-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Regression fixes for exynos542x and exynos5433 SoCs
- use of fallthrough; attribute for s3c24xx
* tag 'clk-v5.8-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
Peng Fan [Thu, 7 May 2020 05:56:17 +0000 (13:56 +0800)]
clk: imx: add imx8m_clk_hw_composite_bus
Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage.
Because the mux switch sequence issue, we could not reuse Peripheral
Clock Slice code, need use composite specific mux operation.
Peng Fan [Thu, 7 May 2020 05:56:16 +0000 (13:56 +0800)]
clk: imx: add mux ops for i.MX8M composite clk
The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
It support target(smart) interface and normal interface. Target interface
is exported for programmer easy to configure ccm root. Normal interface
is also exported, but we not use it in our driver, because it will
introduce more complexity compared with target interface.
The mux in the upper pic is not the target interface MUX, target
interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7],
you are actually writing SEL_A or SEL_B depends on the internal
counter which will also control the internal "mux".
The target interface simplified as below which is used by Linux Kernel:
CLK[0-7]--->MUX-->Gate-->pre_div-->post_div
A requirement of the Target Interface's software is that the
target clock source is active, it means when setting SEL_A, the
current input clk to SEL_A must be active, same to SEL_B.
We touch target interface, but hardware logic actually also need
configure normal interface.
There will be system hang, when doing the following steps:
The initial state:
SEL_A/SEL_B are both sourcing from clk0, the internal counter
choose SEL_A.
1. switch mux from clk0 to clk1
The hardware logic will choose SEL_B and configure SEL_B to clk1.
SEL_A no changed.
2. gate off clk0
Disable clk0, then the input to SEL_A is off.
3. swtich from clk1 to clk2
The hardware logic will choose SEL_A and configure SEL_A to clk2,
however the current SEL_A input clk0 is off, the system hang.
The solution to fix the issue is in step 1, write twice to
target interface MUX, it will make SEL_A/SEL_B both sources
from clk1, then no need to care about the state of clk0. And
finally system performs well.
dt-bindings: clock: renesas: mstp: Convert to json-schema
Convert the Renesas Clock Pulse Generator (CPG) Module Stop (MSTP)
Clocks Device Tree binding documentation to json-schema.
Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Replace the obsolete example for R-Car H2 by an example that is still
valid.
Peng Fan [Thu, 7 May 2020 05:56:13 +0000 (13:56 +0800)]
clk: imx8mp: Define gates for pll1/2 fixed dividers
Inspried from
commit e9f69c27cd20 ("clk: imx8mn: Define gates for pll1/2 fixed dividers")
On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.
Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 7 May 2020 05:56:12 +0000 (13:56 +0800)]
clk: imx: imx8mp: fix pll mux bit
Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll
driver for glitchless freq setting following spec. If exposing the
bit, that means pll driver and clk driver has two paths to touch
this bit, which is wrong.
So use EXT_BYPASS bit here.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 7 May 2020 05:56:11 +0000 (13:56 +0800)]
clk: imx8m: drop clk_hw_set_parent for A53
The parent settings have been moved to dtsi, we no need to
set parent here. And clk_hw_set_parent will trigger lockdep warning,
because this api not have prepare_lock.
Reported-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Szyprowski [Tue, 19 May 2020 10:26:52 +0000 (12:26 +0200)]
clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
Mark the SCLK clock for Exynos5433 I2S1 device with IGNORE_UNUSED flag to
match its behaviour with SCLK clock for AUD_I2S (I2S0) device until
a proper fix for Exynos I2S driver is ready.
This fixes the following synchronous abort issue revealed by the probe
order change caused by the commit f02961d6a769 ("of: platform: Batch
fwnode parsing when adding all top level devices")
dt-bindings: clock: renesas: div6: Convert to json-schema
Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
json-schema.
Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Update the example to match reality.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200507075026.31941-1-geert+renesas@glider.be
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