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2 years agofeat(lib/psa): add read_measurement API
Mate Toth-Pal [Mon, 24 Oct 2022 13:15:10 +0000 (15:15 +0200)]
feat(lib/psa): add read_measurement API

This API is added for testing purposes. It makes possible to write test
cases that read measurements back after extending them, and compare
them to expected results.

Change-Id: Iec447d972fdd54a56ab933a065476e0f4d35a6fc
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
2 years agoMerge "docs(spm): update threat model" into integration
Manish Pandey [Mon, 21 Nov 2022 18:12:00 +0000 (19:12 +0100)]
Merge "docs(spm): update threat model" into integration

2 years agoMerge "docs(qemu): document steps to run in OpenCI" into integration
Manish Pandey [Mon, 21 Nov 2022 17:55:23 +0000 (18:55 +0100)]
Merge "docs(qemu): document steps to run in OpenCI" into integration

2 years agodocs(spm): update threat model
Madhukar Pappireddy [Fri, 14 Oct 2022 21:06:00 +0000 (16:06 -0500)]
docs(spm): update threat model

Update SPM threat model for possible threats, from malicious
endpoints, related to interrupt management. The mitigations
are based on the guidance provided in FF-A v1.1 EAC0 spec.

Change-Id: Ib9e26e3f1c60fe3a2734a67de1dcf1cea4883d38
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2 years agodocs(qemu): document steps to run in OpenCI
Harrison Mutai [Tue, 15 Nov 2022 18:28:18 +0000 (18:28 +0000)]
docs(qemu): document steps to run in OpenCI

Add details on how to run QEMU in OpenCI, and what tests are currently
supported.

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e4eb64a58c766519ff7dcac4841ae75c3934e

2 years agoMerge "fix(intel): fix UART baud rate and clock" into integration
Sandrine Bailleux [Mon, 21 Nov 2022 13:57:10 +0000 (14:57 +0100)]
Merge "fix(intel): fix UART baud rate and clock" into integration

2 years agofix(intel): fix UART baud rate and clock
Sieu Mun Tang [Fri, 1 Jul 2022 01:08:57 +0000 (09:08 +0800)]
fix(intel): fix UART baud rate and clock

Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353

2 years agoMerge "docs(changelog): changelog for v2.8 release" into integration
Manish Pandey [Fri, 18 Nov 2022 17:28:52 +0000 (18:28 +0100)]
Merge "docs(changelog): changelog for v2.8 release" into integration

2 years agoMerge "fix(docs): add v2.9 release schedule" into integration
Joanna Farley [Fri, 18 Nov 2022 16:47:14 +0000 (17:47 +0100)]
Merge "fix(docs): add v2.9 release schedule" into integration

2 years agofix(docs): add v2.9 release schedule
Joanna Farley [Fri, 18 Nov 2022 00:33:16 +0000 (02:33 +0200)]
fix(docs): add v2.9 release schedule

Signed-off-by: Joanna Farley <Joanna.Farley@arm.com>
Change-Id: I082461d7d21f63e3b8cbee37e8f01b8128e4b5a0

2 years agoMerge changes I97687f18,I91d5718b into integration
Olivier Deprez [Thu, 17 Nov 2022 10:14:05 +0000 (11:14 +0100)]
Merge changes I97687f18,I91d5718b into integration

* changes:
  docs(spm): interrupt handling guidance FF-A v1.1 EAC0
  docs(spm): partition runtime model and schedule modes

2 years agoMerge changes from topic "ja/spm_doc" into integration
Olivier Deprez [Thu, 17 Nov 2022 09:04:49 +0000 (10:04 +0100)]
Merge changes from topic "ja/spm_doc" into integration

* changes:
  docs(spm): ff-a v1.1 indirect message
  docs(spm): s-el0 partition support update

2 years agodocs(spm): interrupt handling guidance FF-A v1.1 EAC0
Madhukar Pappireddy [Mon, 3 Oct 2022 23:09:32 +0000 (18:09 -0500)]
docs(spm): interrupt handling guidance FF-A v1.1 EAC0

This patch documents the actions taken by Hafnium SPMC in response
to non-secure and secure interrupts.

Change-Id: I97687f188ca97aeb255e3e5b55d44ddf5d66b6e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2 years agodocs(changelog): changelog for v2.8 release
laurenw-arm [Tue, 15 Nov 2022 16:15:34 +0000 (10:15 -0600)]
docs(changelog): changelog for v2.8 release

Change-Id: I1d99ea46ad527993ee786c34a67f94d74470f960
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2 years agodocs(spm): partition runtime model and schedule modes
Madhukar Pappireddy [Mon, 3 Oct 2022 19:26:48 +0000 (14:26 -0500)]
docs(spm): partition runtime model and schedule modes

This patch documents the support for partition runtime models, call
chains and schedule modes in Hafnium SPMC.

Change-Id: I91d5718bb2c21d475499e402f6f27076930336cb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2 years agoMerge "docs(marvell): fix typo 8K => A8K" into integration
Madhukar Pappireddy [Wed, 16 Nov 2022 17:13:48 +0000 (18:13 +0100)]
Merge "docs(marvell): fix typo 8K => A8K" into integration

2 years agodocs(spm): ff-a v1.1 indirect message
J-Alves [Wed, 26 Oct 2022 12:46:37 +0000 (13:46 +0100)]
docs(spm): ff-a v1.1 indirect message

Update secure partition manager documentation to include
FF-A v1.1 indirect messaging implementation.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ifbca45347f775080ef98ac896d31650204318ba4

2 years agoMerge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration
Manish V Badarkhe [Wed, 16 Nov 2022 15:18:54 +0000 (16:18 +0100)]
Merge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration

* changes:
  docs: add top level section numbering
  docs(build): clarify getting started section
  docs(build): clarify docs building instructions
  fix(docs): prevent a sphinx warning
  fix(docs): prevent a virtual environment from failing a build

2 years agoMerge "docs(spm): update FF-A manifest binding" into integration
Olivier Deprez [Wed, 16 Nov 2022 14:39:08 +0000 (15:39 +0100)]
Merge "docs(spm): update FF-A manifest binding" into integration

2 years agodocs: add top level section numbering
Boyan Karatotev [Thu, 27 Oct 2022 14:12:36 +0000 (15:12 +0100)]
docs: add top level section numbering

Top level sections are not numbered. Adding numbers makes referring to
sections easier. For example the Maintainers page changes from
"about/3.1" to simply "1.3.1".

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If90a18ee8d6a6858d58f0687f31ea62b69399e04

2 years agodocs(build): clarify getting started section
Boyan Karatotev [Thu, 27 Oct 2022 13:47:18 +0000 (14:47 +0100)]
docs(build): clarify getting started section

The Getting started section is very difficult to follow. Building the
fip comes before building the files it needs, the BL33 requirement is
given in a somewhat hand wavy way, and the Arm Developer website
download provides a lot of targets and the guide is not clear which ones
are needed on download.

Swapping the initial build and supporting tools sections makes the flow
more natural and the supporting tools section then becomes clear.
Explicitly mentioning the GCC targets avoids confusion for people less
familiar with the project (eg. new starters).

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I02e88f8c279db6d8eda68f634e8473c02b733963

2 years agodocs(build): clarify docs building instructions
Boyan Karatotev [Thu, 27 Oct 2022 12:55:12 +0000 (13:55 +0100)]
docs(build): clarify docs building instructions

Using virtual environments with pip is a generally recommended good
practice but the docs do not acknowledge it. As a result fresh installs
might fail builds due to missing $PATH entries. The Prerequisites
section is also a bit verbose which is difficult to read.

This patch adds the virtual environment mention and clarifies wording.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iea447fb59dc471a502454650c8548192d93ba879

2 years agofix(docs): prevent a sphinx warning
Boyan Karatotev [Thu, 27 Oct 2022 10:56:40 +0000 (11:56 +0100)]
fix(docs): prevent a sphinx warning

Some newer versions of sphinx (tried on v5.3) will warn about language
being None which will fail the build. Change it to the default (en) to
prevent this.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie0570481f42aeb293e885ca936e0765f6cb299a8

2 years agofix(docs): prevent a virtual environment from failing a build
Boyan Karatotev [Thu, 27 Oct 2022 10:28:23 +0000 (11:28 +0100)]
fix(docs): prevent a virtual environment from failing a build

sphinx-build is passed a blanket "." to build all docs. However, if a
virtual environment is placed within the docs directory, sphinx will try
to build it which will fail due to some weird files it has.

This excludes the most common virtual environment directories from the
build to prevent this.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ieeb14cfc5730d21c986611feb0ed379c58dfcae2

2 years agoMerge "fix(zynqmp): resolve coverity warnings" into integration
Joanna Farley [Wed, 16 Nov 2022 00:04:17 +0000 (01:04 +0100)]
Merge "fix(zynqmp): resolve coverity warnings" into integration

2 years agofix(zynqmp): resolve coverity warnings
HariBabu Gattem [Fri, 7 Oct 2022 07:07:49 +0000 (00:07 -0700)]
fix(zynqmp): resolve coverity warnings

Fix for coverity issues in pm_service component.
Fixed compilation error for versal platform.

Change-Id: I948f01807e67ad1e41021557e040dcbfb7b3a39e
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Signed-off-by: Naman Patel <naman.patel@amd.com>
2 years agoMerge "fix(docs): unify referenced Ubuntu versions" into integration
Madhukar Pappireddy [Tue, 15 Nov 2022 21:25:46 +0000 (22:25 +0100)]
Merge "fix(docs): unify referenced Ubuntu versions" into integration

2 years agofix(docs): unify referenced Ubuntu versions
Boyan Karatotev [Tue, 15 Nov 2022 17:39:22 +0000 (17:39 +0000)]
fix(docs): unify referenced Ubuntu versions

Documentation is inconsistent when referring to Ubuntu versioning.
Change this to a single reference that is consistent with the stated
version for TF-A tests.

The change was tested with a full build on a clean install of Ubuntu 20.04.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibb135ed938e9d92332668fa5caf274cf61b822d3

2 years agoMerge "fix(rockchip): align fdt buffer on 8 bytes" into integration
Manish Pandey [Tue, 15 Nov 2022 11:18:39 +0000 (12:18 +0100)]
Merge "fix(rockchip): align fdt buffer on 8 bytes" into integration

2 years agodocs(spm): s-el0 partition support update
J-Alves [Wed, 26 Oct 2022 10:00:28 +0000 (11:00 +0100)]
docs(spm): s-el0 partition support update

S-EL0 partitions already support indirect messaging and notifications
so add that to supported features.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I08e04593653ba38a2b82395f6f2d3ca7b212d494

2 years agofix(rockchip): align fdt buffer on 8 bytes
Quentin Schulz [Mon, 14 Nov 2022 16:40:33 +0000 (17:40 +0100)]
fix(rockchip): align fdt buffer on 8 bytes

Since commit 94b2f94bd632 ("feat(libfdt): upgrade libfdt source files"),
8-byte alignment of the FDT address is enforced to follow the DT
standard.

Rockchip implementation of params_early_setup loads the FDT address as
passed by the bootloader into a buffer. This buffer is currently made of
uint8_t which means it is not 8-byte aligned and might result in
fdt_open_into failing.

Instead, let's make this buffer uint64_t to make it 8-byte aligned.

Cc: Quentin Schulz <foss+tf-a@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Change-Id: Ifcf0e0cf4000e3661d76d3c3a2fe3921f7fe44b9

2 years agoMerge changes I256959d7,I721376bf into integration
Manish Pandey [Mon, 14 Nov 2022 14:54:27 +0000 (15:54 +0100)]
Merge changes I256959d7,I721376bf into integration

* changes:
  fix(cpus): remove plat_can_cmo check for aarch32
  fix(cpus): update doc and check for plat_can_cmo

2 years agoMerge "refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE" into integration
Manish Pandey [Mon, 14 Nov 2022 14:40:06 +0000 (15:40 +0100)]
Merge "refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE" into integration

2 years agofix(cpus): remove plat_can_cmo check for aarch32
Okash Khawaja [Mon, 14 Nov 2022 13:02:12 +0000 (13:02 +0000)]
fix(cpus): remove plat_can_cmo check for aarch32

We don't need CONDITIONAL_CMO for aarch32 so let's remove it.

Signed-off-by: Okash Khawawja <okash@google.com>
Change-Id: I256959d7005df21a850ff7791c8188ea01f5c53b

2 years agofix(cpus): update doc and check for plat_can_cmo
Okash Khawaja [Mon, 14 Nov 2022 12:50:30 +0000 (12:50 +0000)]
fix(cpus): update doc and check for plat_can_cmo

plat_can_cmo must not clobber x1 but the doc doesn't mention that. This
patch updates the doc to mention x1. It also adds check for plat_can_cmo
to `dcsw_op_louis` which was missed out in original patch.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I721376bf3726520d0d5b0df0f33f98ce92257287

2 years agorefactor(stm32mp1): remove STM32MP_USE_STM32IMAGE
Yann Gautier [Mon, 14 Nov 2022 13:14:48 +0000 (14:14 +0100)]
refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE

The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.

Change-Id: I04452453ed84567b0de39e900594a81526562259
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2 years agoMerge changes from topic "stm32mp1-trusted-boot" into integration
Manish Pandey [Mon, 14 Nov 2022 13:11:55 +0000 (14:11 +0100)]
Merge changes from topic "stm32mp1-trusted-boot" into integration

* changes:
  docs(st): update documentation for TRUSTED_BOARD_BOOT
  fix(build): ensure that the correct rule is called for tools
  feat(stm32mp1): add the platform specific build for tools
  fix(stm32mp13-fdts): remove secure status
  feat(stm32mp1-fdts): add CoT and fuse references for authentication
  feat(stm32mp1): add a check on TRUSTED_BOARD_BOOT with secure chip
  feat(stm32mp1): add the decryption support
  feat(stm32mp1): add the TRUSTED_BOARD_BOOT support
  feat(stm32mp1): update ROM code API for header v2 management
  feat(stm32mp1): remove unused function from boot API
  refactor(stm32mp1): remove authentication using STM32 image mode
  fix(fconf): fix type error displaying disable_auth
  feat(tbbr): increase PK_DER_LEN size
  fix(auth): correct sign-compare warning
  feat(auth): allow to verify PublicKey with platform format PK
  feat(cert-create): update for ECDSA brainpoolP256r/t1 support
  feat(stm32mp1): add RNG initialization in BL2 for STM32MP13
  feat(st-crypto): remove BL32 HASH driver usage
  feat(stm32mp1): add a stm32mp crypto library
  feat(st-crypto): add STM32 RNG driver
  feat(st-crypto): add AES decrypt/auth by SAES IP
  feat(st-crypto): add ECDSA signature check with PKA
  feat(st-crypto): update HASH for new hardware version used in STM32MP13

2 years agodocs(st): update documentation for TRUSTED_BOARD_BOOT
Lionel Debieve [Thu, 6 Oct 2022 07:00:14 +0000 (09:00 +0200)]
docs(st): update documentation for TRUSTED_BOARD_BOOT

Update the documentation to indicate commands needed for
TRUSTED_BOARD_BOOT management.

Change-Id: I7b8781eaa7f8b6b8d675a625c7ff2e1ee767222a
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofix(build): ensure that the correct rule is called for tools
Lionel Debieve [Mon, 14 Nov 2022 10:05:09 +0000 (11:05 +0100)]
fix(build): ensure that the correct rule is called for tools

In case of platform specific usage for both fiptool or certtool,
we need to ensure that the Makefile will use the correct rule
to generate the binary. Add the explicit call to the "all" rule.

Change-Id: I9724b63e01b3497daaedb9365c7d6a494aac9561
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1): add the platform specific build for tools
Lionel Debieve [Thu, 6 Oct 2022 06:54:23 +0000 (08:54 +0200)]
feat(stm32mp1): add the platform specific build for tools

Add cert_create and fiptool specific files to add the platform
addons to the generic tools.

Change-Id: Ifa600241cdf32b495cc65edccddab47c3796b77d
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofix(stm32mp13-fdts): remove secure status
Lionel Debieve [Thu, 6 Oct 2022 06:52:30 +0000 (08:52 +0200)]
fix(stm32mp13-fdts): remove secure status

Remove the secure status for PKA and SAES entries.
The peripherals are used in BL2 at EL3, context will
remain secure only.

Change-Id: I79d95bc55a9afd27f295249936d7bc332c777f5e
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1-fdts): add CoT and fuse references for authentication
Lionel Debieve [Thu, 6 Oct 2022 06:51:32 +0000 (08:51 +0200)]
feat(stm32mp1-fdts): add CoT and fuse references for authentication

Add the stm32mp1 CoT description file. Include the TRUSTED_BOARD_BOOT
entry in the platform device tree file.
Add the missing public root key reference for stm32mp15 and the
encryption key reference for stm32mp13.

Change-Id: I0ae2454979a3df6dd3e4361510317742e8fbc109
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1): add a check on TRUSTED_BOARD_BOOT with secure chip
Lionel Debieve [Wed, 5 Oct 2022 14:52:09 +0000 (16:52 +0200)]
feat(stm32mp1): add a check on TRUSTED_BOARD_BOOT with secure chip

Add a security check to enforce the usage of TRUSTED_BOARD_BOOT
on closed device. It will guarantee the secure bootchain.

Change-Id: Id6120d0e5041e8f2d3866e5710876ec96b6d0216
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1): add the decryption support
Lionel Debieve [Wed, 5 Oct 2022 14:51:12 +0000 (16:51 +0200)]
feat(stm32mp1): add the decryption support

Add the decryption support for STM32MP1 binaries.
Decryption is limited to the BL32 loaded images.

Limitation: STM32MP15 doesn't support the feature.

Change-Id: I96800bac7b22109f8471eb2953fc0dc269fc4fd1
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1): add the TRUSTED_BOARD_BOOT support
Lionel Debieve [Wed, 5 Oct 2022 14:47:03 +0000 (16:47 +0200)]
feat(stm32mp1): add the TRUSTED_BOARD_BOOT support

Add the support of the TRUSTED_BOARD_BOOT to authenticate the loaded
FIP using platform CoT management.
It adds TBB platform definition, redefining the standard image ID in
order to decrease requested size in BL2 binary.
Authentication will use mbedTLS library for parsing certificate
configured with a platform configuration.

Change-Id: I9da66b915c5e9e9293fccfce92bef2434da1e430
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1): update ROM code API for header v2 management
Lionel Debieve [Wed, 5 Oct 2022 14:31:28 +0000 (16:31 +0200)]
feat(stm32mp1): update ROM code API for header v2 management

Add the new definition field for authentication used in header V2
on STM32MP13.

Change-Id: Id8f0c2584ca9b74b0d21d82c9a98d286500548c4
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1): remove unused function from boot API
Lionel Debieve [Wed, 5 Oct 2022 14:29:38 +0000 (16:29 +0200)]
feat(stm32mp1): remove unused function from boot API

Remove old library access from ROM library that is no more
used.

Change-Id: I9b91f1efd6ff9d311b69ca36f60474f01268c221
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agorefactor(stm32mp1): remove authentication using STM32 image mode
Lionel Debieve [Wed, 5 Oct 2022 14:22:07 +0000 (16:22 +0200)]
refactor(stm32mp1): remove authentication using STM32 image mode

Remove deprecated authentication mode to use the FIP authentication
based on TBBR requirements. It will use the new crypto library.

Change-Id: I95c7baa64ba42c370ae136f59781f2a7a4c7f507
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofix(fconf): fix type error displaying disable_auth
Lionel Debieve [Wed, 5 Oct 2022 09:40:15 +0000 (11:40 +0200)]
fix(fconf): fix type error displaying disable_auth

disable_auth is defined as uint32_t and must be displayed
as an unsigned int.

lib/fconf/fconf_tbbr_getter.c:
In function â€˜fconf_populate_tbbr_dyn_config’:
include/common/debug.h:46:41: error:
format â€˜%d’ expects argument of type â€˜int’, but argument 3 has
 type â€˜uint32_t’ {aka â€˜unsigned int’} [-Werror=format=]
   46 | #define LOG_MARKER_WARNING              "\x1e"  /* 30 */
      |                                         ^~~~~~
include/common/debug.h:77:32: note:
 in expansion of macro â€˜LOG_MARKER_WARNING’
   77 | # define WARN(...) tf_log(LOG_MARKER_WARNING __VA_ARGS__)
      |                           ^~~~~~~~~~~~~~~~~~
lib/fconf/fconf_tbbr_getter.c:47:17: note:
in expansion of macro â€˜WARN’
   47 |                 WARN("Invalid value for `%s` cell %d\n",
      |                 ^~~~
include/common/debug.h:48:41: error:
format â€˜%d’ expects argument of type â€˜int’, but argument 5 has
 type â€˜uint32_t’ {aka â€˜unsigned int’} [-Werror=format=]
   48 | #define LOG_MARKER_VERBOSE              "\x32"  /* 50 */
      |                                         ^~~~~~
include/common/debug.h:58:32: note:
in definition of macro â€˜no_tf_log’
   58 |                 tf_log(fmt, ##__VA_ARGS__);     \
      |                        ^~~
include/common/debug.h:91:35: note:
in expansion of macro â€˜LOG_MARKER_VERBOSE’
   91 | # define VERBOSE(...)
      |           no_tf_log(LOG_MARKER_VERBOSE __VA_ARGS__)
      |                     ^~~~~~~~~~~~~~~~~~
lib/fconf/fconf_tbbr_getter.c:74:9: note:
in expansion of macro â€˜VERBOSE’
   74 |    VERBOSE("%s%s%s %d\n","FCONF: `tbbr.", "disable_auth",
      |    ^~~~~~~
cc1: all warnings being treated as errors

Change-Id: I0164ddfe511406cc1a8d014a368ef3e3c5f8cd27
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(tbbr): increase PK_DER_LEN size
Nicolas Toromanoff [Tue, 17 Nov 2020 09:03:40 +0000 (10:03 +0100)]
feat(tbbr): increase PK_DER_LEN size

Public key brainpool ECDSA DER certificate are 92 byte long.
OID for brainpool curve are 1 byte bigger than the one for NIST curve.

Change-Id: Ifad51da3c576d555da9fc519d2df3d9a0e6ed91b
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
2 years agofix(auth): correct sign-compare warning
Nicolas Toromanoff [Wed, 23 Dec 2020 15:01:25 +0000 (16:01 +0100)]
fix(auth): correct sign-compare warning

Correct the warning due to comparison between signed and
unsigned variable.

drivers/auth/mbedtls/mbedtls_x509_parser.c: In function 'get_ext':
drivers/auth/mbedtls/mbedtls_x509_parser.c:120:30:
error: comparison of integer expressions of different
signedness: 'int' and 'size_t' {aka 'unsigned int'}
[-Werror=sign-compare]
120 | if ((oid_len == strlen(oid_str)) && !strcmp(oid, oid_str)) {
    |              ^~

Change-Id: Ic12527f5f92a34e925bee3047c168eacf5e99d8a
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
2 years agofeat(auth): allow to verify PublicKey with platform format PK
Nicolas Toromanoff [Mon, 9 Nov 2020 11:14:52 +0000 (12:14 +0100)]
feat(auth): allow to verify PublicKey with platform format PK

In some platform the digest of the public key saved in the OTP is not
the digest of the exact same public key buffer needed to check the
signature. Typically, platform checks signature using the DER ROTPK
whereas some others add some related information. Add a new platform
weak function to transform the public key buffer used by
verify_signature to a platform specific public key.

Mark this new weak function as deprecated as it will be replaced
by another framework implementation.

Change-Id: I71017b41e3eca9398cededf317ad97e9b511be5f
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(cert-create): update for ECDSA brainpoolP256r/t1 support
Lionel Debieve [Mon, 14 Nov 2022 10:03:42 +0000 (11:03 +0100)]
feat(cert-create): update for ECDSA brainpoolP256r/t1 support

Updated cert_tool to be able to select brainpool P256r/t1
or NIST prim256v1 curve for certificates signature.

Change-Id: I6e800144697069ea83660053b8ba6e21c229243a
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agoMerge changes I5838964f,Id752c1cc,Idd42d5a2,Iff4680cd,I2b1801a7, ... into integration
Manish Pandey [Mon, 14 Nov 2022 10:17:27 +0000 (11:17 +0100)]
Merge changes I5838964f,Id752c1cc,Idd42d5a2,Iff4680cd,I2b1801a7, ... into integration

* changes:
  fix(mt8188): add mmap entry for CPU idle SRAM
  fix(mt8188): refine gic init flow after system resume
  fix(mt8186): fix the DRAM voltage after the system resumes
  feat(mt8188): add audio support
  refactor(mt8195): use ptp3 common drivers
  feat(mt8188): add support for PTP3
  feat(mt8188): enable MTK_PUBEVENT_ENABLE

2 years agofeat(stm32mp1): add RNG initialization in BL2 for STM32MP13
Nicolas Le Bayon [Wed, 2 Dec 2020 15:23:49 +0000 (16:23 +0100)]
feat(stm32mp1): add RNG initialization in BL2 for STM32MP13

Initialize RNG driver at platform level for STM32MP13.

Change-Id: I64832de43e5f6559a12e26680142db54c88f0b9e
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
2 years agofeat(st-crypto): remove BL32 HASH driver usage
Lionel Debieve [Tue, 4 Oct 2022 12:28:57 +0000 (14:28 +0200)]
feat(st-crypto): remove BL32 HASH driver usage

Remove unused mode for HASH driver. The driver will only be
used in BL2 scope.

Change-Id: I1fce09cdaa9da0c11554ac5f73433b4bee776011
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(stm32mp1): add a stm32mp crypto library
Lionel Debieve [Wed, 5 Oct 2022 14:16:50 +0000 (16:16 +0200)]
feat(stm32mp1): add a stm32mp crypto library

Add the crypto library for STM32MP1 to use STM32 hardware
accelerators.

Change-Id: I0bbb941001242a6fdc47514ab3efe07b12249285
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(st-crypto): add STM32 RNG driver
Yann Gautier [Thu, 18 Apr 2019 12:47:35 +0000 (14:47 +0200)]
feat(st-crypto): add STM32 RNG driver

This driver manages the STM32 Random Number Generator
peripheral.

Change-Id: I4403ebb2dbdaa8df993a4413f1ef48eeba00427c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofeat(st-crypto): add AES decrypt/auth by SAES IP
Nicolas Toromanoff [Fri, 18 Sep 2020 07:19:11 +0000 (09:19 +0200)]
feat(st-crypto): add AES decrypt/auth by SAES IP

Add code to be able to use STMicroelectronics SAES IP. This driver
can manage many AES algorithms (CBC, ECB, CCM, GCM). It will be used
by the authenticated decryption framework (AES-GCM only).

Change-Id: Ibd4030719fb12877dcecd5d2c395d13b4b15c260
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
2 years agofeat(st-crypto): add ECDSA signature check with PKA
Nicolas Toromanoff [Wed, 30 Sep 2020 15:36:45 +0000 (17:36 +0200)]
feat(st-crypto): add ECDSA signature check with PKA

Add code to be able to use STMicroelectronics PKA peripheral
in the authentication framework.

Change-Id: Ifeafe84c68db483cd18674f2280576cc065f92ee
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
2 years agofeat(st-crypto): update HASH for new hardware version used in STM32MP13
Nicolas Toromanoff [Tue, 22 Dec 2020 12:54:51 +0000 (13:54 +0100)]
feat(st-crypto): update HASH for new hardware version used in STM32MP13

Introduce new flag to manage hardware version.
STM32MP15 currently uses the HASH_V2 and STM32MP13 uses the HASH_V4.
For STM32_HASH_V4: remove MD5 algorithm (no more supported) and
add SHA384 and SHA512.

For STM32_HASH_V2: no change.

Change-Id: I3a9ae9e38249a2421c657232cb0877004d04dae1
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2 years agofix(mt8188): add mmap entry for CPU idle SRAM
Liju-Clr Chen [Fri, 11 Nov 2022 01:51:51 +0000 (09:51 +0800)]
fix(mt8188): add mmap entry for CPU idle SRAM

CPU PM driver accesses CPU idle SRAM during the system suspend
process. The region of CPU idle SRAM needs to be added as mmap entry.
Otherwise, the execption would occur.

BUG=b:244215539
TEST=Test of suspend resume passes.

Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Change-Id: I5838964fd9cb1b833e4006e2123febb4a4601003

2 years agofix(mt8188): refine gic init flow after system resume
James Liao [Fri, 23 Sep 2022 08:37:59 +0000 (16:37 +0800)]
fix(mt8188): refine gic init flow after system resume

Call gicv3_distif_init() instead of mt_gic_init() in
armv8_2_mcusys_pwr_on_common(). This is to prevent
gicv3_rdistif_init() and gicv3_cpuif_enable() from being called twice
in the power-on flow. gicv3_rdistif_init() and gicv3_cpuif_enable()
are called in later armv8_2_cpu_pwr_on_common().

BUG=b:244215539
TEST=Suspend Resume Test pass

Change-Id: Id752c1ccbb9eab277ed6278c2dd90a051a894146
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
2 years agofix(mt8186): fix the DRAM voltage after the system resumes
Allen-KH Cheng [Tue, 8 Nov 2022 10:40:27 +0000 (18:40 +0800)]
fix(mt8186): fix the DRAM voltage after the system resumes

The DRAM power supply must sustain at 0.8V after the system resumes.
Otherwise, unexpected errors would occur. Therefore, we update the
DRAM voltage to 0.8v in PMIC voltage wrap table.

BUG=b:253537849
TEST=Suspend Resume Test

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: Idd42d5a2d646468822e391e48d01d870c3b7f0d3

2 years agofeat(mt8188): add audio support
Trevor Wu [Tue, 20 Sep 2022 06:50:36 +0000 (14:50 +0800)]
feat(mt8188): add audio support

For MT8188, MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS is required for normal
mode switch.
  - Add audio common code and chip specific code.
  - Add new id (MTK_SIP_AUDIO_CONTROL) to mtk_sip_def.h.
  - Enable for MT8188.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: Iff4680cd0b520b2b519ecf30ecafe100f147cc62

2 years agorefactor(mt8195): use ptp3 common drivers
Liju-Clr Chen [Thu, 3 Nov 2022 11:49:23 +0000 (19:49 +0800)]
refactor(mt8195): use ptp3 common drivers

Some 8195 ptp3 drivers are the same in plat/mediatek/drivers/ptp3, so
add this patch to reuse them.

Change-Id: I2b1801a73b6a2979e20d49d314c57f663dc5bf04
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
2 years agofeat(mt8188): add support for PTP3
Riven Chen [Mon, 17 Oct 2022 05:11:27 +0000 (13:11 +0800)]
feat(mt8188): add support for PTP3

Add PTP3 driver to protect CPU from excessive voltage drop in CPU
heavy loading.

Signed-off-by: Riven Chen <riven.chen@mediatek.corp-partner.google.com>
Change-Id: I394096be43e1d1d615f99b22f38f0b3ae0bb40c1

2 years agofeat(mt8188): enable MTK_PUBEVENT_ENABLE
Rex-BC Chen [Fri, 14 Oct 2022 08:19:25 +0000 (16:19 +0800)]
feat(mt8188): enable MTK_PUBEVENT_ENABLE

Enable MTK_PUBEVENT_ENABLE for subscribing CPUPM events. This
patch also corrects the header file naming.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iabd89a4ead21ccafa833390367484bfea5d351f6

2 years agoMerge "refactor(security): add OpenSSL 1.x compatibility" into integration
Manish V Badarkhe [Fri, 11 Nov 2022 18:59:58 +0000 (19:59 +0100)]
Merge "refactor(security): add OpenSSL 1.x compatibility" into integration

2 years agorefactor(security): add OpenSSL 1.x compatibility
Juan Pablo Conde [Tue, 25 Oct 2022 23:41:02 +0000 (19:41 -0400)]
refactor(security): add OpenSSL 1.x compatibility

When updated to work with OpenSSL 3.0, the host tools lost their
compatibility with previous versions (1.x) of OpenSSL. This is
mainly due to the fact that 1.x APIs became deprecated in 3.0 and
therefore their use cause compiling errors. In addition, updating
for a newer version of OpenSSL meant improving the stability
against security threats. However, although version 1.1.1 is
now deprecated, it still receives security updates, so it would
not imply major security issues to keep compatibility with it too.

This patch adds backwards compatibility with OpenSSL 1.x versions
by adding back 1.x API code. It defines a macro USING_OPENSSL3,
which will select the appropriate OpenSSL API version depending on
the OpenSSL library path chosen (which is determined by the
already-existing OPENSSL_DIR variable).

In addition, cleanup items were packed in functions and moved to
the proper modules in order to make the code more maintainable and
legible.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I8deceb5e419edc73277792861882404790ccd33c

2 years agoMerge "fix(docs): add LTS maintainers" into integration
Manish Pandey [Fri, 11 Nov 2022 17:40:39 +0000 (18:40 +0100)]
Merge "fix(docs): add LTS maintainers" into integration

2 years agoMerge "feat(cpus): make cache ops conditional" into integration
Bipin Ravi [Fri, 11 Nov 2022 16:49:20 +0000 (17:49 +0100)]
Merge "feat(cpus): make cache ops conditional" into integration

2 years agofix(docs): add LTS maintainers
Bipin Ravi [Fri, 11 Nov 2022 05:13:01 +0000 (23:13 -0600)]
fix(docs): add LTS maintainers

Adding the  maintainers for the TF-A LTS releases.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I683885b8b52c0d004218fa52f71a245bd26b1229

2 years agoMerge "fix(pmu): add sensible default for MDCR_EL2" into integration
Manish Pandey [Fri, 11 Nov 2022 15:56:30 +0000 (16:56 +0100)]
Merge "fix(pmu): add sensible default for MDCR_EL2" into integration

2 years agoMerge "build: deprecate Arm TC0 FVP platform" into integration
Manish V Badarkhe [Fri, 11 Nov 2022 13:06:03 +0000 (14:06 +0100)]
Merge "build: deprecate Arm TC0 FVP platform" into integration

2 years agofix(pmu): add sensible default for MDCR_EL2
Boyan Karatotev [Wed, 26 Oct 2022 14:10:39 +0000 (15:10 +0100)]
fix(pmu): add sensible default for MDCR_EL2

When TF-A is set to save and restore EL2 registers it initially zeroes
all of them so that it does not leak any information. However,
MDCR_EL2.HPMN of 0 is poorly defined when FEAT_HPMN0 is not implemented.
Set it to its hardware reset value so that lower ELs don't inherit a
wrong value.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8055005ef9b6eaafefa13b62a0b41289079fdd23

2 years agobuild: deprecate Arm TC0 FVP platform
Manish V Badarkhe [Fri, 11 Nov 2022 09:36:29 +0000 (09:36 +0000)]
build: deprecate Arm TC0 FVP platform

Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superseded by the TC1 and TC2 platforms,
which are already supported in TF-A and CI repositories.

Change-Id: I0269816a6ee733f732669027eae4e14cd60b6084
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 years agoMerge "fix(cpus): workaround for Cortex-A77 erratum 2743100" into integration
Bipin Ravi [Fri, 11 Nov 2022 04:35:21 +0000 (05:35 +0100)]
Merge "fix(cpus): workaround for Cortex-A77 erratum 2743100" into integration

2 years agoMerge "fix(docs): update maintainers list" into integration
Joanna Farley [Fri, 11 Nov 2022 00:02:44 +0000 (01:02 +0100)]
Merge "fix(docs): update maintainers list" into integration

2 years agofix(docs): update maintainers list
Manish Pandey [Mon, 7 Nov 2022 15:18:38 +0000 (15:18 +0000)]
fix(docs): update maintainers list

As part of release process revisit list of maintainers to keep
it updated.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I63b87265a6bff00ad05d8b3b7cad694cdf48e9ea

2 years agoMerge "chore(docs): fix broken url references to arm procedure call" into integration
Manish V Badarkhe [Thu, 10 Nov 2022 18:25:01 +0000 (19:25 +0100)]
Merge "chore(docs): fix broken url references to arm procedure call" into integration

2 years agoMerge changes from topic "mp/ras_refactoring" into integration
Olivier Deprez [Thu, 10 Nov 2022 16:46:21 +0000 (17:46 +0100)]
Merge changes from topic "mp/ras_refactoring" into integration

* changes:
  docs: document do_panic() and panic() helper functions
  fix(ras): restrict RAS support for NS world

2 years agochore(docs): fix broken url references to arm procedure call
Govindraj Raja [Thu, 10 Nov 2022 15:27:35 +0000 (15:27 +0000)]
chore(docs): fix broken url references to arm procedure call

Couple for urls under section: `5.6. Use of built-in C and libc
data types` from docs has broken urls since the new arm procedure
call doc is moved to be part of `ARM-software/abi-aa`.

Change-Id: Ied184ed56c8335d4cbc687e56962439091a18e42
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2 years agoMerge changes from topic "mp/ras_refactoring" into integration
Manish Pandey [Thu, 10 Nov 2022 16:22:39 +0000 (17:22 +0100)]
Merge changes from topic "mp/ras_refactoring" into integration

* changes:
  fix(debug): decouple "get_el_str()" from backtrace
  fix(bl31): harden check in delegate_async_ea

2 years agofix(cpus): workaround for Cortex-A77 erratum 2743100
Boyan Karatotev [Tue, 1 Nov 2022 11:22:12 +0000 (11:22 +0000)]
fix(cpus): workaround for Cortex-A77 erratum 2743100

Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb
before the isb in the power down sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1152370/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8e49a2dac8611f31ace249a17ae7a90cd60e742a

2 years agoMerge changes from topic "ffa_el3_spmc_fixes" into integration
Joanna Farley [Thu, 10 Nov 2022 12:46:33 +0000 (13:46 +0100)]
Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
  fix(el3-spmc): check descriptor size for overflow
  fix(el3-spmc): fix location of fragment length check
  fix(el3-spmc): fix detection of overlapping memory regions
  fix(el3-spmc): fix incomplete reclaim validation

2 years agofeat(cpus): make cache ops conditional
Okash Khawaja [Fri, 4 Nov 2022 12:38:01 +0000 (12:38 +0000)]
feat(cpus): make cache ops conditional

When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset. Similarly, debug recovery mode of DynamIQ
cluster ensures that contents of the shared L3 cache are also not
invalidated upon transition to On mode.

Booting cores in debug recovery mode means booting with caches disabled
and preserving the caches until a point where software can dump the
caches and retrieve their contents. TF-A however unconditionally cleans
and invalidates caches at multiple points during boot. This can lead to
memory corruption as well as loss of cache contents to be used for
debugging.

This patch fixes this by calling a platform hook before performing CMOs
in helper routines in cache_helpers.S. The platform hook plat_can_cmo is
an assembly routine which must not clobber x2 and x3, and avoid using
stack. The whole checking is conditional upon `CONDITIONAL_CMO` which
can be set at compile time.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193

2 years agoMerge "chore(docs): move deprecated platforms information around" into integration
Manish Pandey [Thu, 10 Nov 2022 11:59:17 +0000 (12:59 +0100)]
Merge "chore(docs): move deprecated platforms information around" into integration

2 years agoMerge "build: warn about RSS driver experimental status" into integration
Sandrine Bailleux [Thu, 10 Nov 2022 06:46:25 +0000 (07:46 +0100)]
Merge "build: warn about RSS driver experimental status" into integration

2 years agoMerge changes from topic "errata" into integration
Madhukar Pappireddy [Wed, 9 Nov 2022 20:20:24 +0000 (21:20 +0100)]
Merge changes from topic "errata" into integration

* changes:
  fix(cpus): workaround for Cortex-A76 erratum 2743102
  fix(cpus): workaround for Neoverse N1 erratum 2743102

2 years agoMerge "refactor(trng): cleanup the existing TRNG support" into integration
Manish V Badarkhe [Wed, 9 Nov 2022 16:30:17 +0000 (17:30 +0100)]
Merge "refactor(trng): cleanup the existing TRNG support" into integration

2 years agoMerge "fix(versal-net): add default values for silicon" into integration
Joanna Farley [Wed, 9 Nov 2022 11:49:28 +0000 (12:49 +0100)]
Merge "fix(versal-net): add default values for silicon" into integration

2 years agoMerge "docs(rme): add instruction to build rmm" into integration
Soby Mathew [Wed, 9 Nov 2022 11:48:38 +0000 (12:48 +0100)]
Merge "docs(rme): add instruction to build rmm" into integration

2 years agoMerge "docs(security): rename Makalu and SB optimisation" into integration
Joanna Farley [Wed, 9 Nov 2022 11:48:23 +0000 (12:48 +0100)]
Merge "docs(security): rename Makalu and SB optimisation" into integration

2 years agoMerge "docs(maintainers): update qti maintainer" into integration
Joanna Farley [Wed, 9 Nov 2022 11:38:48 +0000 (12:38 +0100)]
Merge "docs(maintainers): update qti maintainer" into integration

2 years agodocs(rme): add instruction to build rmm
Shruti Gupta [Wed, 2 Nov 2022 11:33:38 +0000 (11:33 +0000)]
docs(rme): add instruction to build rmm

Add documentation to build and run TF-A with RMM,
Linux kernel and TFTF Realm Payload.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I951b41a144aabe0fec16eb933d7f005a65f06fb2

2 years agoMerge "docs: add link to DCO" into integration
Manish V Badarkhe [Wed, 9 Nov 2022 09:43:51 +0000 (10:43 +0100)]
Merge "docs: add link to DCO" into integration

2 years agofix(versal-net): add default values for silicon
Michal Simek [Sat, 5 Nov 2022 22:39:47 +0000 (15:39 -0700)]
fix(versal-net): add default values for silicon

Add missing default value for silicon.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Iac7d4db17a29a148298e9e3bd3eb3f74cafe7bc1

2 years agochore(docs): move deprecated platforms information around
Sandrine Bailleux [Tue, 8 Nov 2022 12:36:42 +0000 (13:36 +0100)]
chore(docs): move deprecated platforms information around

We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:

 a) the process for deprecating a platform port;
 b) the list of deprecated platforms to this day.

I think it makes more sense to move b) to the platforms ports landing
page, such that it is more visible.

This also has the nice effect to move the 'Deprecated platforms' title
as the last entry of the 'Platform ports' table of contents, like so:

 - Platform ports
   - 1. Allwinner ARMv8 SoCs
   - 2. Arm Development Platforms
     ...
   - 39. Broadcom Stingray
   - Deprecated platforms

instead of it being lost in the middle of supported platform ports.

Regarding a), this gets moved under the "Processes & Policies" section.
More specifically, it gets clubbed with the existing platform
compatibility policy. The combined document gets renamed into a
"Platforms Ports Policy" document.

Change-Id: I6e9ce2abc68b8a8ac88e7bd5f21749c14c9a2af6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2 years agoMerge "chore(docs): refresh platform ports landing page" into integration
Sandrine Bailleux [Wed, 9 Nov 2022 09:28:07 +0000 (10:28 +0100)]
Merge "chore(docs): refresh platform ports landing page" into integration