drm: of: Properly try all possible cases for bridge/panel detection
While bridge/panel detection was initially relying on the usual
port/ports-based of graph detection, it was recently changed to
perform the lookup on any child node that is not port/ports
instead when such a node is available, with no fallback on the
usual way.
This results in breaking detection when a child node is present
but does not contain any panel or bridge node, even when the
usual port/ports-based of graph is there.
In order to support both situations properly, this commit reworks
the logic to try both options and not just one of the two: it will
only return -EPROBE_DEFER when both have failed.
Christian König [Fri, 11 Mar 2022 09:32:26 +0000 (10:32 +0100)]
dma-buf/sync-file: fix warning about fence containers
The dma_fence_chain containers can show up in sync_files as well resulting in
warnings that those can't be added to dma_fence_array containers when merging
multiple sync_files together.
Solve this by using the dma_fence_unwrap iterator to deep dive into the
contained fences and then add those flatten out into a dma_fence_array.
Christian König [Mon, 24 Jan 2022 13:03:24 +0000 (14:03 +0100)]
dma-buf: Add dma_fence_array_for_each (v2)
Add a helper to iterate over all fences in a dma_fence_array object.
v2 (Jason Ekstrand)
- Return NULL from dma_fence_array_first if head == NULL. This matches
the iterator behavior of dma_fence_chain_for_each in that it iterates
zero times if head == NULL.
- Return NULL from dma_fence_array_next if index > array->num_fences.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210610210925.642582-2-jason@jlekstrand.net Signed-off-by: Christian König <christian.koenig@amd.com>
Jani Nikula [Wed, 23 Mar 2022 10:04:38 +0000 (12:04 +0200)]
drm/edid: fix CEA extension byte #3 parsing
Only an EDID CEA extension has byte #3, while the CTA DisplayID Data
Block does not. Don't interpret bogus data for color formats.
For most displays it's probably an unlikely scenario you'd have a CTA
DisplayID Data Block without a CEA extension, but they do exist.
Fixes: e28ad544f462 ("drm/edid: parse CEA blocks embedded in DisplayID") Cc: <stable@vger.kernel.org> Cc: Shawn C Lee <shawn.c.lee@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220323100438.1757295-1-jani.nikula@intel.com
Cooper Chiou [Thu, 24 Mar 2022 06:12:18 +0000 (14:12 +0800)]
drm/edid: check basic audio support on CEA extension block
Tag code stored in bit7:5 for CTA block byte[3] is not the same as
CEA extension block definition. Only check CEA block has
basic audio support.
v3: update commit message.
Cc: stable@vger.kernel.org Cc: Jani Nikula <jani.nikula@intel.com> Cc: Shawn C Lee <shawn.c.lee@intel.com> Cc: intel-gfx <intel-gfx@lists.freedesktop.org> Signed-off-by: Cooper Chiou <cooper.chiou@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> Fixes: e28ad544f462 ("drm/edid: parse CEA blocks embedded in DisplayID") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220324061218.32739-1-shawn.c.lee@intel.com
drm/selftest: plane_helper: Put test structures in static storage
Clang warns on certain 32-bit architectures:
drivers/gpu/drm/selftests/test-drm_plane_helper.c:76:5: warning: stack frame size (1064) exceeds limit (1024) in 'igt_check_plane_state' [-Wframe-larger-than]
int igt_check_plane_state(void *ignored)
^
1 warning generated.
The structures in igt_check_plane_state() total 1008 bytes, so any small
amount of inlining will cause the stack frame to exceed the 32-bit limit
of 1024, triggering the warning.
Move these structures to static storage, which dramatically reduces the
amount of stack space in igt_check_plane_state(). There is no testing
impact, as igt_check_plane_state() is only called once in the driver.
Zack Rusin [Fri, 18 Mar 2022 17:43:32 +0000 (13:43 -0400)]
drm/ttm: Fix a kernel oops due to an invalid read
The res is initialized here only if there's no errors so passing it to
ttm_resource_fini in the error paths results in a kernel oops. In the
error paths, instead of the unitialized res, we have to use to use
node->base on which ttm_resource_init was called.
Signed-off-by: Zack Rusin <zackr@vmware.com> Fixes: de3688e469b0 ("drm/ttm: add ttm_resource_fini v2") Cc: Christian König <christian.koenig@amd.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Martin Krastev <krastevm@vmware.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220318174332.440068-6-zack@kde.org
Lang Yu [Mon, 7 Mar 2022 03:47:45 +0000 (11:47 +0800)]
drm/amdgpu: fix a wrong ib reference
It should be p->job->ibs[j] instead of p->job->ibs[i] here.
Fixes: cdc7893fc93f19 ("drm/amdgpu: use job and ib structures directly in CS parsers") Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Wed, 9 Mar 2022 19:46:36 +0000 (05:46 +1000)]
Merge tag 'exynos-drm-next-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
New feature
- Add BGR pixel format support for FIMD device. As for this,
this patch uses undocumented register, WIN_RGB_ORDER, but
it is safe because product kernels have been using same
register.
Matthew Auld [Thu, 3 Mar 2022 10:02:29 +0000 (10:02 +0000)]
drm/i915/gtt: reduce overzealous alignment constraints for GGTT
Currently this will enforce both 2M alignment and padding for any LMEM
pages inserted into the GGTT. However, this was only meant to be applied
to the compact-pt layout with the ppGTT. For the GGTT we can reduce the
alignment and padding to 64K.
Bspec: 45015 Fixes: 87bd701ee268 ("drm/i915: enforce min GTT alignment for discrete cards") Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Robert Beckett <bob.beckett@collabora.com> Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220303100229.839282-1-matthew.auld@intel.com
(cherry picked from commit c64fa77dd4609cb8cd53fbb73b02434ae8212c7a) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Rob Clark [Tue, 8 Mar 2022 18:48:44 +0000 (10:48 -0800)]
drm/msm/gpu: Fix crash on devices without devfreq support (v2)
Avoid going down devfreq paths on devices where devfreq is not
initialized.
v2: Change has_devfreq() logic [Dmitry]
Reported-by: Linux Kernel Functional Testing <lkft@linaro.org> Reported-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Fixes: 6aa89ae1fb04 ("drm/msm/gpu: Cancel idle/boost work on suspend") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220308184844.1121029-1-robdclark@gmail.com
Dan Carpenter [Mon, 7 Mar 2022 13:31:05 +0000 (16:31 +0300)]
drm/msm/adreno: fix cast in adreno_get_param()
These casts need to happen before the shift. The only time it would
matter would be if "rev.core" is >= 128. In that case the sign bit
would be extended and we do not want that.
Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspace") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Link: https://lore.kernel.org/r/20220307133105.GA17534@kili Signed-off-by: Rob Clark <robdclark@chromium.org>
Ville Syrjälä [Mon, 14 Feb 2022 10:55:31 +0000 (12:55 +0200)]
drm/i915: Fix the async flip wm0/ddb optimization
The current implementation of the async flip wm0/ddb optimization
does not work at all. The biggest problem is that we skip the
whole intel_pipe_update_{start,end}() dance and thus never actually
complete the commit that is trying to do the wm/ddb change.
To fix this we need to move the do_async_flip flag to the crtc
state since we handle commits per-pipe, not per-plane.
Also since all planes can now be included in the first/last
"async flip" (which gets converted to a sync flip to do the
wm/ddb mangling) we need to be more careful when checking if
the plane state is async flip comptatible. Only planes doing
the async flip should be checked and other planes are perfectly
fine not adhereing to any async flip related limitations.
However for subsequent commits which are actually going do the
async flip in hardware we want to make sure no other planes
are in the state. That should never happen assuming we did our
job correctly, so we'll toss in a WARN to make sure we catch
any bugs here.
Ville Syrjälä [Mon, 14 Feb 2022 10:55:30 +0000 (12:55 +0200)]
drm/i915: Check async flip capability early on
Since the async flip state check is done very late and
thus it can see potentially all the planes in the state
(due to the wm/ddb optimization) we need to move the
"can the requested plane do async flips at all?" check
much earlier. For this purpose we introduce
intel_async_flip_check_uapi() that gets called early during
the atomic check.
And for good measure we'll throw in a couple of basic checks:
- is the crtc active?
- was a modeset flagged?
- is+was the plane enabled?
Though atm all of those should be guaranteed by the fact
that the async flip can only be requested through the legacy
page flip ioctl.
Ville Syrjälä [Mon, 14 Feb 2022 10:55:29 +0000 (12:55 +0200)]
drm/i915: Don't skip ddb allocation if data_rate==0
data_rate==0 no longer means a plane is disabled, it could
also mean we want to use the minimum ddb allocation for it.
Hence we can't bail out early during ddb allocation or
else we'll simply forget to allocate any ddb for such planes.
Ville Syrjälä [Wed, 23 Feb 2022 13:13:03 +0000 (15:13 +0200)]
drm/i915: Avoid negative shift due to bigjoiner_pipes==0
bigjoiner_pipes==0 leads bigjoiner_master_pipe() to
do BIT(ffs(0)-1) which is undefined behaviour. The code should
actually still work fine since the only place we provoke
that is intel_crtc_bigjoiner_slave_pipes() and it'll bitwise
AND the result with 0, so doesn't really matter what we get
out of bigjoiner_master_pipe(). But best not provoke undefined
behaviour anyway.
Philip Yang [Fri, 4 Mar 2022 14:33:27 +0000 (09:33 -0500)]
drm/amdkfd: Add format attribute to kfd_smi_event_add
To enable compiler type-checked against the format string in callers.
All warnings (new ones prefixed by >>):
>> warning: function 'kfd_smi_event_add' might be a candidate for
'gnu_printf' format attribute [-Wsuggest-attribute=format]
Fixes: d58b8a99cbb8 ("drm/amdkfd: Add SMI add event helper") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhi Wang [Tue, 22 Feb 2022 15:05:32 +0000 (10:05 -0500)]
drm/i915/gvt: add the missing mdev attribute "name"
The mdev attribute "name" is required by some middle software, e.g.
KubeVirt, an open source SW that manages VM on Kubernetes cluster uses
the mdev sysfs directory/file structure to discover mediated device in
nodes in the cluster.
v2:
- Fix the missing defination in gvt_type_attrs. (Zhenyu)
Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Hui Chun Ong <hui.chun.ong@intel.com> Cc: Terrence Xu <terrence.xu@intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com> Link: http://patchwork.freedesktop.org/patch/msgid/20220222150532.9090-1-zhi.a.wang@intel.com Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Rob Clark [Fri, 4 Mar 2022 20:21:45 +0000 (12:21 -0800)]
drm/msm: Fix dirtyfb refcounting
refcount_t complains about 0->1 transitions, which isn't *quite* what we
wanted. So use dirtyfb==1 to mean that the fb is not connected to any
output that requires dirtyfb flushing, so that we can keep the underflow
and overflow checking.
Rob Clark [Thu, 24 Feb 2022 22:23:21 +0000 (14:23 -0800)]
drm/msm: Add MSM_SUBMIT_FENCE_SN_IN
Add a way for userspace to specify the sequence number fence used to
track completion of the submit. As the seqno fence is simply an
incrementing counter which is local to the submitqueue, it is easy for
userspace to know the next value.
This is useful for native userspace drivers in a vm guest, as the guest
to host roundtrip can have high latency. Assigning the fence seqno in
the guest userspace allows the guest to continue without waiting for
response from the host.
Rob Clark [Fri, 4 Mar 2022 00:52:17 +0000 (16:52 -0800)]
drm/msm/a6xx: Zap counters across context switch
Any app controlled perfcntr collection (GL_AMD_performance_monitor, etc)
does not require counters to maintain state across context switches. So
clear them if systemwide profiling is not active.
Rob Clark [Fri, 4 Mar 2022 00:52:16 +0000 (16:52 -0800)]
drm/msm: Add SYSPROF param (v2)
Add a SYSPROF param for system profiling tools like Mesa's pps-producer
(perfetto) to control behavior related to system-wide performance
counter collection. In particular, for profiling, one wants to ensure
that GPU context switches do not effect perfcounter state, and might
want to suppress suspend (which would cause counters to lose state).
v2: Swap the order in msm_file_private_set_sysprof() [sboyd] and
initialize the sysprof_active refcount to one (because the under/
overflow checking in refcount_t doesn't expect a 0->1 transition)
meaning that values greater than 1 means sysprof is active.
Rob Clark [Fri, 4 Mar 2022 00:52:15 +0000 (16:52 -0800)]
drm/msm: Add SET_PARAM ioctl
It was always expected to have a use for this some day, so we left a
placeholder. Now we do. (And I expect another use in the not too
distant future when we start allowing userspace to allocate GPU iova.)
Christian König [Tue, 1 Mar 2022 14:13:15 +0000 (15:13 +0100)]
drm/amdgpu: initialize the vmid_wait with the stub fence
This way we don't need to check for NULL any more.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 1 Mar 2022 08:57:41 +0000 (09:57 +0100)]
drm/amdgpu: properly embed the IBs into the job
We now have standard macros for that.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 1 Mar 2022 08:51:58 +0000 (09:51 +0100)]
drm/amdgpu: use job and ib structures directly in CS parsers
Instead of providing the ib index provide the job and ib pointers directly to
the patch and parse functions for UVD and VCE.
Also move the set/get functions for IB values to the IB declerations.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 21 Feb 2022 12:51:17 +0000 (13:51 +0100)]
drm/amdgpu: header cleanup
No function change, just move a bunch of definitions from amdgpu.h into
separate header files.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jingwen Chen [Wed, 2 Mar 2022 09:44:38 +0000 (17:44 +0800)]
drm/amd/amdgpu: set disabled vcn to no_schduler
[Why]
after the reset domain introduced, the sched.ready will be init after
hw_init, which will overwrite the setup in vcn hw_init, and lead to
vcn ib test fail.
[How]
set disabled vcn to no_scheduler
Fixes: 5fd8518d187ed0 ("drm/amdgpu: Move scheduler init to after XGMI is ready") Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 21 Feb 2022 01:45:59 +0000 (20:45 -0500)]
drm/amd/display: 3.2.175
drm/amd/display: 3.2.175
This version brings along following fixes:
- Remove invalid RDPCS Programming in DAL
- Make functional resource functions non-static
- Reset VIC if HDMI_VIC is present
- Add frame alternate 3D & restrict HW packed on dongles
- Reg to turn on/off PSR Power seq in FSM
- Modify plane removal sequence to avoid hangs
- Pass HostVM enable flag into DCN3.1 DML
- DC Validation failures
- Program OPP before ODM
- Refactor fixed VS w/a for PHY tests
- Pass deep sleep disabled allow info to dmub fw
- Refine the EDID override
- [FW Promotion] Release 0.0.106.0
- Add verify_link_cap back for hdmi
Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Mon, 21 Feb 2022 00:02:20 +0000 (19:02 -0500)]
drm/amd/display: add verify_link_cap back for hdmi
[why]
hdmi specific: add verify link cap after retrive link cap.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sun, 20 Feb 2022 16:37:09 +0000 (11:37 -0500)]
drm/amd/display: [FW Promotion] Release 0.0.106.0
Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
jinzh [Thu, 10 Feb 2022 14:50:06 +0000 (22:50 +0800)]
drm/amd/display: refine the EDID override
[Why]
We already get the SBIOS EDID via ACPI on KMD,
but after that, we just use the monitor EDID to set it HDR caps
[How]
Make the SBIOS EDID override to read_edid()
That can change the read EDID caps from the right EDID
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: jinzh <jinzh@github.amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Robin Chen [Thu, 17 Feb 2022 11:19:22 +0000 (19:19 +0800)]
drm/amd/display: Pass deep sleep disabled allow info to dmub fw
[Why]
The deep sleep mode need to be disabled in some PSR scenario.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Robin Chen <robin.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
George Shen [Thu, 17 Feb 2022 21:01:15 +0000 (16:01 -0500)]
drm/amd/display: Refactor fixed VS w/a for PHY tests
[Why/How]
Refactor original w/a to unify naming and
simplify logic. This also re-enables the code
that was previously skipped due to the
disabling of the previous workaround logic.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: George Shen <George.Shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wesley Chalmers [Tue, 8 Feb 2022 23:12:49 +0000 (18:12 -0500)]
drm/amd/display: Program OPP before ODM
[WHY]
HW expects OPP to be configured before ODM is enabled.
Failure to do so can cause errors.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Wed, 16 Feb 2022 22:01:18 +0000 (17:01 -0500)]
drm/amd/display: Pass HostVM enable flag into DCN3.1 DML
[WHY]
Calculations differ with HostVM enabled/disabled, causing underflow in
configs with high refresh displays + scaling due to lower available BW
[HOW]
Check riommu_active in order to pass correct HostVM enablement to DML
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Jücker [Sat, 29 Jan 2022 22:01:53 +0000 (23:01 +0100)]
drm/exynos: fimd: add BGR support for exynos4/5
In the downstream kernels for exynos4 and exynos5 devices, there is an
undocumented register that controls the order of the RGB output. It can
be set to either normal order or reversed, which enables BGR support for
those SoCs.
This patch enables the BGR support for all the SoCs that were found to
have at least one device with this logic in the corresponding downstream
kernels.
Signed-off-by: Martin Jücker <martin.juecker@gmail.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Marek Szyprowski [Mon, 24 Jan 2022 13:52:46 +0000 (14:52 +0100)]
drm/exynos: Search for TE-gpio in DSI panel's node
TE-gpio, if defined, is placed in the panel's node, not the parent DSI
node. Change the devm_gpiod_get_optional() to gpiod_get_optional() and
pass proper device node to it. The code already has a proper cleanup
path, so it looks that the devm_* variant has been applied accidentally
during the conversion to gpiod API.
Fixes: ee6c8b5afa62 ("drm/exynos: Replace legacy gpio interface for gpiod interface") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixed a typo. Signed-off-by: Inki Dae <inki.dae@samsung.com>
Marek Szyprowski [Fri, 21 Jan 2022 10:00:39 +0000 (11:00 +0100)]
drm/exynos: Don't fail if no TE-gpio is defined for DSI driver
TE-gpio is optional and if it is not found then gpiod_get_optional()
returns NULL. In such case the code will continue and try to convert NULL
gpiod to irq what in turn fails. The failure is then propagated and driver
is not registered.
Fix this by returning early from exynos_dsi_register_te_irq() if no
TE-gpio is found.
Fixes: ee6c8b5afa62 ("drm/exynos: Replace legacy gpio interface for gpiod interface") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Lad Prabhakar [Wed, 22 Dec 2021 19:01:34 +0000 (19:01 +0000)]
drm/exynos: gsc: Use platform_get_irq() to get the interrupt
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypassed the hierarchical setup and messed up the
irq chaining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().
Lad Prabhakar [Wed, 22 Dec 2021 19:01:33 +0000 (19:01 +0000)]
drm/exynos/fimc: Use platform_get_irq() to get the interrupt
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypassed the hierarchical setup and messed up the
irq chaining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().
Lad Prabhakar [Wed, 22 Dec 2021 19:01:32 +0000 (19:01 +0000)]
drm/exynos/exynos_drm_fimd: Use platform_get_irq_byname() to get the interrupt
platform_get_resource_byname(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypassed the hierarchical setup and messed up the
irq chaining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq_byname().
Lad Prabhakar [Wed, 22 Dec 2021 19:01:31 +0000 (19:01 +0000)]
drm/exynos: mixer: Use platform_get_irq() to get the interrupt
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypassed the hierarchical setup and messed up the
irq chaining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().
Lad Prabhakar [Wed, 22 Dec 2021 19:01:30 +0000 (19:01 +0000)]
drm/exynos/exynos7_drm_decon: Use platform_get_irq_byname() to get the interrupt
platform_get_resource_byname(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypassed the hierarchical setup and messed up the
irq chaining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq_byname().
Dave Airlie [Fri, 4 Mar 2022 04:30:28 +0000 (14:30 +1000)]
Merge tag 'drm-msm-next-2022-03-01' of https://gitlab.freedesktop.org/drm/msm into drm-next
We're experimenting a bit with the process this time, with Dmitry
collecting display patches and merging them into msm-next with me
handling the gpu/etc side of things. Summary of interesting new bits
and pieces
* dpu + dp support for sc8180x
* dp support for sm8350
* dpu + dsi support for qcm2290
* 10nm dsi phy tuning support
* bridge support for dp encoder
* gpu support for additional 7c3 SKUs
* assorted cleanups and fixes
Dave Airlie [Fri, 4 Mar 2022 04:16:30 +0000 (14:16 +1000)]
Merge tag 'drm-intel-gt-next-2022-03-03' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
Cross-subsystem Changes:
- drm-next backmerge for buddy allocator changes
Driver Changes:
- Skip i915_perf init for DG2 as it is not yet enabled (Ram)
- Add missing workarounds for DG2 (Clint)
- Add 64K page/align support for platforms like DG2 that require it (Matt A, Ram, Bob)
- Add accelerated migration support for DG2 (Matt A)
- Add flat CCS support for XeHP SDV (Abdiel, Ram)
- Add Compute Command Streamer (CCS) engine support for XeHP SDV (Michel,
Daniele, Aravind, Matt R)
- Don't support parallel submission on compute / render (Matt B, Matt R)
- Disable i915 build on PREEMPT_RT until RT behaviour fixed (Sebastian)
- Remove RPS interrupt support for TGL+ (Jose)
- Fix S/R with PM_EARLY for non-GTT mappable objects on DG2 (Matt, Lucas)
- Skip stolen memory init if it is fully reserved (Jose)
- Use iosys_map for GuC data structures that may be in LMEM BAR or SMEM (Lucas)
- Do not complain about stale GuC reset notifications for banned contexts (John)
- Move context descriptor fields to intel_lrc.h
- Start adding support for small BAR (Matt A)
- Clarify vma lifetime (Thomas)
- Simplify subplatform detection on TGL (Jose)
- Correct the param count for unset GuC SLPC param (Vinay, Umesh)
- Read RP_STATE_CAP correctly on Gen12 with GuC SLPC (Vinay)
- Initialize GuC submission locks and queues early (Daniele)
- Fix GuC flag query helper function to not modify state (John)
- Drop fake lmem support now we have real hardware available (Lucas)
- Move misplaced W/A to their correct locations (Srinivasan)
- Use get_reset_domain() helper (Tejas)
- Move context descriptor fields to intel_lrc.h (Matt R)
- Selftest improvements (Matt A)
Dave Airlie [Fri, 4 Mar 2022 03:41:52 +0000 (13:41 +1000)]
Merge tag 'drm-misc-next-2022-03-03' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v5.18:
UAPI Changes:
Cross-subsystem Changes:
- Improve performance of some fbdev ops, in some cases up to 6x faster.
Core Changes:
- Some small DP fixes.
- Find panels in subnodes of OF devices, and add of_get_drm_panel_display_mode
to retrieve mode.
- Add drm_object_property_get_default_value and use it for resetting
zpos in plane state reset, removing the need for individual drivers
to do it.
- Same for color encoding and color range props.
- Update panic handling todo doc.
- Add todo that format conversion helpers should be sped up similarly to fbdev ops.
Driver Changes:
- Add panel orientation property to simpledrm for quirked panels.
- Assorted small fixes to tiny/repaper, nouveau, stm, omap, ssd130x.
- Add crc support to stm/ltdc.
- Add MIPI DBI compatible SPI driver
- Assorted small fixes to tiny panels and bridge drivers.
- Add AST2600 support to aspeed.
Laurent Pinchart [Wed, 26 Jan 2022 20:13:23 +0000 (22:13 +0200)]
drm: rcar-du: Drop LVDS device tree backward compatibility
The rcar-du driver goes to great lengths to preserve device tree
backward compatibility for the LVDS encoders by patching old device
trees at runtime.
The last R-Car Gen2 platform was converted to the new bindings commit edb0c3affe5214a2 ("ARM: dts: r8a7793: Convert to new LVDS DT bindings"),
in v4.17, and the last RZ/G1 platform converted in commit 6a6a797625b5fe85 ("ARM: dts: r8a7743: Convert to new LVDS DT bindings"),
in v5.0. Both are older than commit 58256143cff7c2e0 ("clk: renesas:
Remove R-Car Gen2 legacy DT clock support"), in v5.5, which removes
support for legacy bindings for clocks. The LVDS compatibility code is
thus not needed anymore. Drop it.
Colin Ian King [Wed, 2 Mar 2022 17:53:09 +0000 (17:53 +0000)]
drm/ssd130x: remove redundant initialization of pointer mode
Pointer mode is being assigned a value that is never read, it is
being re-assigned later with a new value. The initialization is
redundant and can be removed.
Cleans up clang scan build warning:
drivers/gpu/drm/solomon/ssd130x.c:582:27: warning: Value stored
to 'mode' during its initialization is never read [deadcode.DeadStores]
Weiguo Li [Wed, 2 Mar 2022 16:17:39 +0000 (00:17 +0800)]
drm/amdgpu: remove redundant null check
Remove the redundant null check since the caller ensures
that 'ctx' is never NULL.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Weiguo Li <liwg06@foxmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Thu, 10 Feb 2022 23:17:39 +0000 (18:17 -0500)]
drm/amd/display: Modify plane removal sequence to avoid hangs.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Danijel Slivka [Wed, 2 Mar 2022 10:29:55 +0000 (11:29 +0100)]
drm/amd/pm: new v3 SmuMetrics data structure for Sienna Cichlid
structure changed in smc_fw_version >= 0x3A4900,
"uint16_t VcnActivityPercentage" replaced with
"uint16_t VcnUsagePercentage0" and "uint16_t VcnUsagePercentage1"
Signed-off-by: Danijel Slivka <danijel.slivka@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Qiang Yu [Tue, 1 Mar 2022 06:11:59 +0000 (14:11 +0800)]
drm/amdgpu: fix suspend/resume hang regression
Regression has been reported that suspend/resume may hang with
the previous vm ready check commit.
So bring back the evicted list check as a temp fix.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1922 Fixes: c1a66c3bc425 ("drm/amdgpu: check vm ready by amdgpu_vm->evicting flag") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Qiang Yu <qiang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Tue, 1 Mar 2022 05:54:42 +0000 (13:54 +0800)]
drm/amdgpu: Move CAP firmware loading to the beginning of PSP firmware list
[Why]
As PSP needs to verify the signature, CAP firmware must be loaded first when PSP loads firmwares.
Otherwise, when DFC feature is enabled, CP firmwares would be loaded failed.
[ 1149.160480] [drm] MM table gpu addr = 0x800022f000, cpu addr = 00000000a62afcea.
[ 1149.209874] [drm] failed to load ucode CP_CE(0x8)
[ 1149.209878] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007)
[ 1149.215914] [drm] failed to load ucode CP_PFP(0x9)
[ 1149.215917] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007)
[ 1149.221941] [drm] failed to load ucode CP_ME(0xA)
[ 1149.221944] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007)
[ 1149.228082] [drm] failed to load ucode CP_MEC1(0xB)
[ 1149.228085] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007)
[ 1149.234209] [drm] failed to load ucode CP_MEC2(0xD)
[ 1149.234212] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007)
[ 1149.242379] [drm] failed to load ucode VCN(0x1C)
[ 1149.242382] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007)
[How]
Move CAP UCODE ID to the beginning of AMDGPU_UCODE_ID enum list.
drm/amdgpu: Bump minor version for hot plug tests enabling.
This will allow to enable the tests only after latest fix
after which the tests passed on my system.
I tested on NV21 standalone and Vega 10 and Polaris as
pair with DRI_PRIME.
It's possible there might be still issues on ASICs i don't
have at my posession but that that the point of enbling
the tests finally - if other people during testing will
encounter errors they will report and I will be able to fix.
The releated merge request for enabling libdrm tests suite is in
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/227
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix sigsev when accessing MMIO on hot unplug.
Protect with drm_dev_enter/exit
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 2 Mar 2022 19:09:07 +0000 (14:09 -0500)]
drm/amdgpu: convert code name to ip version for noretry set
Use IP version rather than codename for noretry set.
Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
yipechai [Thu, 17 Feb 2022 07:40:12 +0000 (15:40 +0800)]
drm/amdgpu: Remove redundant .ras_fini initialization in some ras blocks
1. Define amdgpu_ras_block_late_fini_default in amdgpu_ras.c as
.ras_fini common function, which is called when
.ras_fini of ras block isn't initialized.
2. Remove the code of using amdgpu_ras_block_late_fini to
initialize .ras_fini in ras blocks.
Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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