André Przywara [Tue, 22 Dec 2020 15:50:26 +0000 (15:50 +0000)]
Merge changes I0c5f32e8,Id49c124c,Idcfe933d into integration
* changes:
allwinner: Use RSB for the PMIC connection on H6
allwinner: Return the PMIC to I2C mode after use
allwinner: Always use a 3MHz RSB bus clock
Graeme Gregory [Wed, 2 Dec 2020 16:24:32 +0000 (16:24 +0000)]
PSCI: fix limit of 256 CPUs caused by cast to unsigned char
In psci_setup.c psci_init_pwr_domain_node() takes an unsigned
char as node_idx which limits it to initialising only the first
256 CPUs. As the calling function does not check for a limit of
256 I think this is a bug so change the unsigned char to
uint16_t and change the cast from the calling site in
populate_power_domain_tree().
Also update the non_cpu_pwr_domain_node structure lock_index
to uint16_t and update the function signature for psci_lock_init()
appropriately.
Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add
a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot
exceed the index value.
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This issue is
present in revisions r0p0 - r4p1 but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.
plat/arm/rdn2: update gic redistributor base address
RD-N2 platform has been updated to use six GIC ITS blocks. This results
in change in base address of the GIC Redistributor to accomodate two
new GIC ITS blocks. Update the base address of GICR to reflect the same.
Mirela Simonovic [Mon, 23 Nov 2020 07:31:14 +0000 (23:31 -0800)]
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I51f2285a79f202cb2ca9f031044002e16dd1e92f
zynqmp: pm: Reimplement pinctrl set/get function EEMI API
Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I21b8fda855aa69090b85d6aaf411e19560201cb5
zynqmp: pm: Implement pinctrl request/release EEMI API
The calls are just passed through to the PMU-FW. Before issuing
other pinctrl functions the pin should be successfully requested.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibce280edebedf779b3962009c274d0b3d928e0e4
Rajan Vaja [Tue, 24 Nov 2020 05:33:39 +0000 (21:33 -0800)]
zynqmp: pm: Update return type in query functions
In pm_query_data() function return type is stored in response so
there is no use of return type. Update return type of function
pm_query_data() from enum pm_ret_status to void. Similarly
update return type of pm_api_clock_get_name() and
pm_api_pinctrl_get_function_name() functions.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Id811926f0b4ebcc472480bb94f3b88109eb036cd
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
- create SPMC manifest file with OP-TEE as SP
- add support for ARM_SPMC_MANIFEST_DTS build option
- add optee entry with ffa as method in tc0.dts
Samuel Holland [Mon, 14 Dec 2020 04:34:10 +0000 (22:34 -0600)]
allwinner: Use RSB for the PMIC connection on H6
RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
either bus.
Change-Id: I0c5f32e88a090c8c5cccb81bd24596b301ab9da7 Signed-off-by: Samuel Holland <samuel@sholland.org>
Samuel Holland [Mon, 14 Dec 2020 04:43:15 +0000 (22:43 -0600)]
allwinner: Return the PMIC to I2C mode after use
This gives the rich OS the flexibility to choose between I2C and RSB
communication. Since a runtime address can only be assigned once after
entering RSB mode, it also lets the rich OS choose any runtime address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id49c124c5e925985fc31c0ba38c7fb6c941aafa8
Samuel Holland [Mon, 14 Dec 2020 04:53:02 +0000 (22:53 -0600)]
allwinner: Always use a 3MHz RSB bus clock
None of the other drivers (Linux, U-Boot, Crust) need to lower the bus
clock frequency to switch the PMIC to RSB mode. That logic is not needed
here, either. The hardware takes care of running this transaction at the
correct bus frequency.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idcfe933df4da75d5fd5a4f3e362da40ac26bdad1
Samuel Holland [Mon, 14 Dec 2020 02:05:11 +0000 (20:05 -0600)]
allwinner: Fix non-default PRELOADED_BL33_BASE
While the Allwinner platform code nominally supported a custom
PRELOADED_BL33_BASE, some references to the BL33 load address used
another constant: PLAT_SUNXI_NS_IMAGE_OFFSET. To allow the DTB search
code to work if a U-Boot BL33 is loaded to a custom address,
consistently use PRELOADED_BL33_BASE. And to avoid this confusion in
the future, remove the other constant.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie6b97ae1fdec95d784676aef39200bef161471b0
Samuel Holland [Mon, 14 Dec 2020 03:56:15 +0000 (21:56 -0600)]
allwinner: Add SPC security setup for H6
The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into a header, and add the missing MMIO base address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I3703868bc595459ecf9568b9d1605cb1be014bf5
Samuel Holland [Mon, 14 Dec 2020 03:44:54 +0000 (21:44 -0600)]
allwinner: Add R_PRCM security setup for H6
H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no effect unless the secure mode e-fuse is blown.
Since we are adding more platform-specific CCU registers, move them to
their own header, and out of the memory map (where they do not belong).
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86
Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in memory map
plat/arm/sgi: add platform id value for rdn2 platform
plat/arm/sgi: platform definitions for upcoming platforms
plat/arm/sgi: refactor header file inclusions
plat/arm/sgi: refactor the inclusion of memory mapping
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.
If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.
This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
Alexei Fedorov [Mon, 7 Dec 2020 16:38:53 +0000 (16:38 +0000)]
TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.
Manish Pandey [Wed, 9 Dec 2020 22:44:44 +0000 (22:44 +0000)]
Merge changes from topic "versal-bug-fixes-and-new-apis" into integration
* changes:
plat: xilinx: versal: Add support of register notifier
plat: xilinx: versal: Add support to get clock rate value
plat: xilinx: versal: Add support of set max latency for the device
plat: versal: Add InitFinalize API call
xilinx: versal: Updated Response of QueryData API call
plat:xilinx:versal: Use defaults when PDI is without sw partitions
plat: xilinx: Mask unnecessary bytes of return error code
xilinx: versal: Skip store/restore of GIC during CPU idle
plat: versal: Update API list in feature check
xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
Olivier Deprez [Wed, 9 Dec 2020 15:08:27 +0000 (15:08 +0000)]
Merge changes from topic "secure_no_primary" into integration
* changes:
spm: provide number of vCPUs and VM size for first SP
spm: remove chosen node from SPMC manifests
spm: move OP-TEE SP manifest DTS to FVP platform
spm: update OP-TEE SP manifest with device-regions node
spm: remove device-memory node from SPMC manifests
Aditya Angadi [Thu, 19 Nov 2020 12:02:41 +0000 (17:32 +0530)]
plat/arm/sgi: adapt to changes in memory map
Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping and other platform specific functionality separately
from the existing platforms.
Aditya Angadi [Thu, 19 Nov 2020 11:48:21 +0000 (17:18 +0530)]
plat/arm/sgi: add platform id value for rdn2 platform
In preparation for adding the board support for RD-N2 platform, add
macros to define the platform id and the corresponding SCMI platform
info for the RD-N2 platform.
Aditya Angadi [Tue, 17 Nov 2020 15:47:58 +0000 (21:17 +0530)]
plat/arm/sgi: platform definitions for upcoming platforms
Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
upcoming platforms, create platform definitions for those platforms.
Aditya Angadi [Wed, 18 Nov 2020 03:02:30 +0000 (08:32 +0530)]
plat/arm/sgi: refactor header file inclusions
Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support for those upcoming RD platforms, refactor the
header file inclusion to allow newer platforms to use a different
set of platform macros.
Aditya Angadi [Wed, 18 Nov 2020 02:57:15 +0000 (08:27 +0530)]
plat/arm/sgi: refactor the inclusion of memory mapping
Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
usable only for existing platforms and let upcoming platforms define
a different set of mmap entries.
Marek Vasut [Sun, 8 Nov 2020 18:13:32 +0000 (19:13 +0100)]
rcar_gen3: drivers: console: Treat log as device memory
The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.
The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf
Ravi Patel [Tue, 18 Sep 2018 09:14:12 +0000 (02:14 -0700)]
zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.
Example:
Consider a case of nand_ref clock which has 2 divisor and 1 mux.
The frequency of mux clock is 1500MHz and default value of div1 and
div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
When driver requests 80MHz for nand_ref clock, clock framework will
adjust the div2 value to 1 (setting div2 value 2 results final clock
to 50MHz which is more inaccurate compare to 100Mhz) which results
final clock to 100MHz.
Ideally the value of div1 and div2 should be updated to 19 and 1
respectively so that final clock goes to around 78MHz.
This patch fixes above problem by allowing change in div1 value.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
Olivier Deprez [Wed, 25 Nov 2020 09:29:41 +0000 (10:29 +0100)]
spm: provide number of vCPUs and VM size for first SP
The primary VM concept is removed from the SPMC.
Update the SPMC manifests with number of Execution Contexts
and SP workspace size for the first Secure Partition (as it
is done for NWd secondary VMs and other SPs).
Yuchen Huang [Sat, 1 Aug 2020 08:23:12 +0000 (16:23 +0800)]
mediatek: mt8192: add uart save and restore api
When system resume, we want to print log as soon as possible.
So we add uart save and restore api, and they will be called
when systtem suspend and resume.
Change-Id: I83b477fd2b39567c9c6b70534ef186993f7053ae Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
G.Pangao [Fri, 6 Nov 2020 01:20:25 +0000 (09:20 +0800)]
mediatek: mt8192: modify sys_cirq driver
1.Modify this driver to make it more complete and more standard.
2.And makes this driver available for more IC services.
3.Solve some bugs in the software.
Manish Pandey [Mon, 7 Dec 2020 11:29:46 +0000 (11:29 +0000)]
Merge changes from topic "marvell-a3k-makefile" into integration
* changes:
plat: marvell: armada: a3k: Simplify check if WTP variable is defined
plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code
plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository
plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
Tejas Patel [Wed, 25 Nov 2020 09:56:57 +0000 (01:56 -0800)]
plat: xilinx: versal: Add support of register notifier
Add support of register notifier.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I41ef4c63abcc9aee552790b843adb25a5fd0c23e
plat: xilinx: versal: Add support to get clock rate value
Add support to get clock's rate value.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d
Tejas Patel [Wed, 25 Nov 2020 09:53:12 +0000 (01:53 -0800)]
plat: xilinx: versal: Add support of set max latency for the device
Add support of set max latency, to change in the maximum powerup latency
requirements for a specific device currently used by Subsystem.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I8749886abb1a7884a42c4d156d89c9cd562a5b1a
Ravi Patel [Mon, 12 Aug 2019 10:10:10 +0000 (03:10 -0700)]
plat: versal: Add InitFinalize API call
Add support to call InitFinalize API in Versal which calls
corresponding LibPM API.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3428b7245b4db1ef6db8a90b7ad20b6e484ed3b2
Rajan Vaja [Mon, 23 Nov 2020 12:13:54 +0000 (04:13 -0800)]
xilinx: versal: Updated Response of QueryData API call
For the current XilPM calls, The handler of IPI returns information
with 16 Bytes data.
So during QueryData API call for the ClockName and PinFunctionName,
response data(name of clock or function) response[0..3] are used to
return name. And status is not being returned for such API.
Updated XilPM calls reply in a consistent way and The handler of IPI
return information with 32Bytes data. Where response[0] always set
to status.
For the version-2 of QueryData API, during call for the ClockName
and PinFunctionName, response data(name of clock or function) get as
response[1...4].
To support both the version of QueryData API, added version based
compatibility by the use of feature check.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I336128bff7bbe659903b0f8ce20ae6da7e3b51b4
Ravi Patel [Mon, 23 Nov 2020 12:19:08 +0000 (04:19 -0800)]
plat: xilinx: Mask unnecessary bytes of return error code
Versal firmware adds extra error codes along with PM error codes
while sending response to driver. This makes incorrect error
identification at driver side.
To fix this, mask the unnecessary error bytes before sending the
error code to the driver.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I18c2f3bd2d067e91344852c2f0c1bafea0e6eb23
Ravi Patel [Fri, 21 Jun 2019 12:00:49 +0000 (05:00 -0700)]
xilinx: versal: Skip store/restore of GIC during CPU idle
GIC registers needs to be stored/restored during system
suspend/resume only and not during CPU idle.
During CPU idle, minimum 1 CPU is in ON state.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I5de2ce3a61bf4260f9385349202b0f592a47aaba
Add below API in feature check list which is actually present in
firmware:
- PM_GET_CHIPID
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98b82da74164f065c8835861f74b0f2855e9bcbf
Ravi Patel [Tue, 30 Jul 2019 11:10:07 +0000 (04:10 -0700)]
xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
Existing code passes ACPU0 to LibPM as node_id in set_wakeup_source()
call because last suspending core will be ACPU0 in most of the case.
Now it may be possible that user may disable the ACPU0 using hot-plug
and after that it suspends Linux. So in that case ACPU0 will not be
last suspending core.
To overcome above scenario, pass the current running processor ID
while calling set_wakeup_source().
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If15354c2150b5bb1305b5f93ca4e8c7a81d59f0a
Pali Rohár [Mon, 23 Nov 2020 18:49:23 +0000 (19:49 +0100)]
plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
These two targets are build by make subprocesses and are independent.
So splitting them into own targets allow make to build them in parallel.
$(TIMBUILD) script depends on $(TIMDDRTOOL) so specify it in Makefile.
Pali Rohár [Mon, 23 Nov 2020 18:45:28 +0000 (19:45 +0100)]
plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
FORCE target is used as a dependency for other file targets which needs to
be always rebuilt. .PHONY target is standard Makefile target which specify
non-file targets and therefore needs to be always rebuilt.
Targets clean, realclean and distclean are .PHONY targets used to remove
built files. Correctly set that mrvl_clean target is prerequisite for these
clean targets to ensure that built files are removed.
Finally this change with usage of FORCE target allows to remove mrvl_clean
hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used
just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess.
Pali Rohár [Mon, 23 Nov 2020 18:14:40 +0000 (19:14 +0100)]
plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
$(WTMI_IMG) is used only by $(MAKE) subprocess in $(DOIMAGEPATH) directory.
So calling truncate on $(WTMI_IMG) after $(MAKE) in $(DOIMAGEPATH) has no
effect and can just damage input file for future usage. Therefore remove
this truncate call.
plat: xilinx: zynqmp: Enable log messages for debug
Save some space by enabling the log messages like bl33 address
only for debug builds. Also check the bl33 and bl32 address and
print only if this is not NULL.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I58d846bf69a75e839eb49abcbb9920af13296886
Tejas Patel [Mon, 23 Nov 2020 07:37:55 +0000 (23:37 -0800)]
plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
For boot health status PMU Global General Storage Register 4 is
used. GGS4 can be used for other purpose along with boot health
status. So, change its name from PM_BOOT_HEALTH_STATUS_REG
to PMU_GLOBAL_GEN_STORAGE4.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I2f5c4c6a161121e7cdb4b9f0f8711d0dad16c372
projects / arm-tf.git / log