Dmitry Mastykin [Thu, 28 Dec 2017 15:19:24 +0000 (18:19 +0300)]
pinctrl: mcp23s08: fix irq setup order
When using mcp23s08 module with gpio-keys, often (50% of boots)
it fails to get irq numbers with message:
"gpio-keys keys: Unable to get irq number for GPIO 0, error -6".
Seems that irqs must be setup before devm_gpiochip_add_data().
Ladislav Michl [Mon, 22 Jan 2018 12:31:11 +0000 (13:31 +0100)]
pinctrl: Forward declare struct device
pinctrl/devinfo.h is using forward declaration from pinctrl/consumer.h
for configurations with CONFIG_PINCTRL defined, however nothing declares
it in the opposite case. Fix this by adding a forward declaration.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Peter Rosin [Wed, 17 Jan 2018 13:34:23 +0000 (14:34 +0100)]
pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping
Without such a range, gpiolib fails with -EPROBE_DEFER, pending the
addition of the range. So, without a range, gpiolib will keep
deferring indefinitely.
There is code duplication between uniphier_conf_pin_drive_get() and
uniphier_conf_pin_drive_set(). Factor out the common code into
uniphier_conf_get_drvctrl_data().
Stefan Agner [Sat, 6 Jan 2018 14:25:50 +0000 (15:25 +0100)]
pinctrl: imx7d: simplify imx7d_pinctrl_probe
Using of_device_get_match_data in imx7d_pinctrl_probe simplifies
the function. Also get rid of the void pointer cast since
imx_pinctrl_probe now accepts const struct imx_pinctrl_soc_info.
Stefan Agner [Sat, 6 Jan 2018 14:25:49 +0000 (15:25 +0100)]
pinctrl: imx: use struct imx_pinctrl_soc_info as a const
For some SoCs the struct imx_pinctrl_soc_info is passed through
of_device_id.data which is const. Most variables are already const
or otherwise not written. However, some fields are modified at
runtime. Move those fields to the dynamically allocated struct
imx_pinctrl.
Bai Ping [Sat, 6 Jan 2018 14:25:53 +0000 (15:25 +0100)]
pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
are available in a separate IOMUXC_SNVS module. Add support for the
IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 8 Jan 2018 07:17:10 +0000 (08:17 +0100)]
Merge tag 'sh-pfc-for-v4.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.16 (take two)
- Add PWM pin groups on various R-Car Gen2 and RZ/G1 SoCs,
- Add missing I2C5 pin groups on R-Car E2 and RZ/G1E,
- Add SATA pin groups on R-Car H3 ES2.0.
Julia Lawall [Tue, 2 Jan 2018 13:28:01 +0000 (14:28 +0100)]
pinctrl: armada-37xx: account for const type of of_device_id.data
The data field of an of_device_id structure has type const void *, so
there is no need for a const-discarding cast when putting const values
into such a structure.
Julia Lawall [Tue, 2 Jan 2018 13:28:04 +0000 (14:28 +0100)]
pinctrl: axp209: account for const type of of_device_id.data
The return value of of_device_get_match_data has type const void *.
The desc field of the pctl structure also has a const type, so there
is no need for the const-discarding cast between them.
Done using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Tue, 2 Jan 2018 13:27:58 +0000 (14:27 +0100)]
pinctrl: at91-pio4: account for const type of of_device_id.data
This driver creates a const structure that it stores in the data field
of an of_device_id array.
Adding const to the declaration of the location that receives the
const value from the data field ensures that the compiler will
continue to check that the value is not modified. Furthermore, the
const-discarding cast on the extraction from the data field is no
longer needed.
Done using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Hans de Goede [Mon, 1 Jan 2018 12:23:57 +0000 (13:23 +0100)]
pinctrl: baytrail: Enable glitch filter for GPIOs used as interrupts
On some systems, some PCB traces attached to GpioInts are routed in such
a way that they pick up enough interference to constantly (many times per
second) trigger.
Enabling glitch-filtering fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Sat, 23 Dec 2017 21:07:30 +0000 (22:07 +0100)]
pinctrl: rockchip: Improve a size determination in rockchip_pinctrl_probe()
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Wed, 20 Dec 2017 11:38:53 +0000 (12:38 +0100)]
pinctrl: adi2: Improve a size determination in two functions
Replace the specification of data structures by variable references
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Wed, 20 Dec 2017 09:22:53 +0000 (10:22 +0100)]
pinctrl/nomadik/abx500: Improve a size determination in abx500_gpio_probe()
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tony Lindgren [Thu, 14 Dec 2017 16:51:15 +0000 (08:51 -0800)]
pinctrl: single: Remove invalid message
Pinctrl single should just show how many pins were found, the physical
address is already in the dev information. So let's remove the wrong
information that claims to show the physical address but really prints
a virtual address that is now hashed.
Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Wed, 20 Dec 2017 09:37:46 +0000 (10:37 +0100)]
Merge tag 'sh-pfc-for-v4.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.16
- Add CAN pin groups on RZ/G1E,
- Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3,
- Add support for the new R-Car V3M SoC,
- Add support for I2C on R-Car D3,
- Small fixes and cleanups.
Quentin Schulz [Wed, 13 Dec 2017 08:55:03 +0000 (09:55 +0100)]
pinctrl: axp209: dereference pointer after it's been set
The number of GPIOs is gotten from a field within the structure
referenced in the of_device.data but it was actually read before it was
retrieved, thus it was dereferencing a null pointer.
Set the number of GPIOs after retrieving of_device.data.
Brian Norris [Tue, 12 Dec 2017 17:43:43 +0000 (09:43 -0800)]
pinctrl: rockchip: enable clock when reading pin direction register
We generally leave the GPIO clock disabled, unless an interrupt is
requested or we're accessing IO registers. We forgot to do this for the
->get_direction() callback, which means we can sometimes [1] get
incorrect results [2] from, e.g., /sys/kernel/debug/gpio.
Enable the clock, so we get the right results!
[1] Sometimes, because many systems have 1 or mor interrupt requested on
each GPIO bank, so they always leave their clock on.
[2] Incorrect, meaning the register returns 0, and so we interpret that
as "input".
Sean Wang [Tue, 12 Dec 2017 06:24:21 +0000 (14:24 +0800)]
pinctrl: mediatek: update MAINTAINERS entry with MediaTek pinctrl driver
I work for MediaTek on maintaining the existing MediaTek SoC whose target
to home gateway such as MT7622 and MT7623 that is reusing MT2701 related
files and will keep adding support for the following such kinds of SoCs
in the future.
Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sean Wang [Tue, 12 Dec 2017 06:24:20 +0000 (14:24 +0800)]
pinctrl: mediatek: add pinctrl driver for MT7622 SoC
Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has
the registers for pinctrl, pinconf and gpio mixed up in the same register
range. However, the IO core for the MT7622 SoC is completely distinct from
anyone of previous MediaTek SoCs which already had support, such as
the hardware internal, register address map and register detailed
definition for each pin.
Therefore, instead, the driver is being newly implemented by reusing
generic methods provided from the core layer with GENERIC_PINCONF,
GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code
simplicity and rid of superfluous code. Where the function of pins
determined by groups is utilized in this driver which can help developers
less confused with what combinations of pins effective on the SoC and even
reducing the mistakes during the integration of those relevant boards.
As the gpio_chip handling is also only a few lines, the driver also
implements the gpio functionality directly through GPIOLIB.
Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sean Wang [Tue, 12 Dec 2017 06:24:19 +0000 (14:24 +0800)]
pinctrl: mediatek: cleanup for placing all drivers under the menu
Since lots of MediaTek drivers had been added, it seems slightly better
for that adding cleanup for placing MediaTek pinctrl drivers under the
independent menu as other kinds of drivers usually was done.
Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: Really force states during suspend/resume
In case a platform only defaults a "default" set of pins, but not a
"sleep" set of pins, and this particular platform suspends and resumes
in a way that the pin states are not preserved by the hardware, when we
resume, we would call pinctrl_single_resume() -> pinctrl_force_default()
-> pinctrl_select_state() and the first thing we do is check that the
pins state is the same as before, and do nothing.
In order to fix this, decouple the actual state change from
pinctrl_select_state() and move it pinctrl_commit_state(), while keeping
the p->state == state check in pinctrl_select_state() not to change the
caller assumptions. pinctrl_force_sleep() and pinctrl_force_default()
are updated to bypass the state check by calling pinctrl_commit_state().
[Linus Walleij]
The forced pin control states are currently only used in some pin
controller drivers that grab their own reference to their own pins.
This is equal to the pin control hogs: pins taken by pin control
devices since there are no corresponding device in the Linux device
hierarchy, such as memory controller lines or unused GPIO lines,
or GPIO lines that are used orthogonally from the GPIO subsystem
but pincontrol-wise managed as hogs (non-strict mode, allowing
simultaneous use by GPIO and pin control). For this case forcing
the state from the drivers' suspend()/resume() callbacks makes
sense and should semantically match the name of the function.
Fixes: e3e5ef096e7f ("pinctrl: API changes to support multiple states per device") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Quentin Schulz [Tue, 5 Dec 2017 14:46:45 +0000 (15:46 +0100)]
pinctrl: axp209: add programmable ADC muxing value
To prepare for patches that will add support for a new PMIC that has a
different GPIO adc muxing value, add an adc_mux within axp20x_pctl
structure and use it.
To prepare for patches that will add support for a new PMIC that has a
different GPIO input status register, add a gpio_status_offset within
axp20x_pctl structure and use it.
Quentin Schulz [Tue, 5 Dec 2017 14:46:43 +0000 (15:46 +0100)]
pinctrl: axp209: rename everything from gpio to pctl
This driver used to do only GPIO features of the GPIOs in X-Powers
AXP20X. Now that we have migrated everything to the pinctrl subsystem
and added pinctrl features, rename everything related to pinctrl from
gpio to pctl to ease the understanding of differences between GPIO
and pinctrl features.
Colin Ian King [Mon, 4 Dec 2017 17:08:15 +0000 (17:08 +0000)]
pinctrl: intel: ensure error return ret is initialized
In the (unlikely) event that community->ngpps is zero, or if every
gpp->gpio_base is less than zero, then an ininitialized value in
ret is returned by function intel_gpio_add_pin_ranges. Fix this by
ensuring ret is initialized to zero. It's a moot point, but I think
it is worthwhile ensuring this corner case is fixed.
Detected by CoverityScan, CID#1462415 ("Uninitialized scalar variable")
Fixes: 42d47291e29d ("pinctrl: intel: Allow custom GPIO base for pad groups") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 2 Dec 2017 11:23:09 +0000 (12:23 +0100)]
pinctrl: gemini: Support drive strength setting
The Gemini pin controller can set drive strength for a few
select groups of pins (not individually). Implement this
for GMAC0 and 1 (ethernet ports), IDE and PCI.
Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Takeshi Kihara [Thu, 16 Nov 2017 03:16:00 +0000 (12:16 +0900)]
pinctrl: sh-pfc: r8a7795-es1: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR16 bit[27:24].
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E.
Fabrizio Castro [Tue, 14 Nov 2017 15:41:17 +0000 (15:41 +0000)]
pinctrl: sh-pfc: r8a7791: Add can_clk function
This patch adds can_clk function to r8a7743/r8a7791 which is cleaner,
and allows for independent configuration.
We keep the can_clk* pins definitions from within can0_groups and
can1_groups for uniformity and backwards compatibility.
Fabrizio Castro [Tue, 14 Nov 2017 15:41:16 +0000 (15:41 +0000)]
pinctrl: sh-pfc: r8a7794: Add can_clk function
This patch adds can_clk function to r8a7745/r8a7794 which is cleaner,
and allows for independent configuration.
We keep the can_clk* pins definitions from within can0_groups and
can1_groups for uniformity and backwards compatibility.
Sergei Shtylyov [Fri, 10 Nov 2017 17:59:01 +0000 (20:59 +0300)]
pinctrl: sh-pfc: Add R8A77970 PFC support
Add the PFC support for the R8A77970 SoC including pin groups for some
on-chip devices such as CAN-FD, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM,
VIN...
Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop EtherAVB for now] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Mika Westerberg [Wed, 29 Nov 2017 13:25:44 +0000 (16:25 +0300)]
pinctrl: intel: Initialize GPIO properly when used through irqchip
When a GPIO is requested using gpiod_get_* APIs the intel pinctrl driver
switches the pin to GPIO mode and makes sure interrupts are routed to
the GPIO hardware instead of IOAPIC. However, if the GPIO is used
directly through irqchip, as is the case with many I2C-HID devices where
I2C core automatically configures interrupt for the device, the pin is
not initialized as GPIO. Instead we rely that the BIOS configures the
pin accordingly which seems not to be the case at least in Asus X540NA
SKU3 with Focaltech touchpad.
When the pin is not properly configured it might result weird behaviour
like interrupts suddenly stop firing completely and the touchpad stops
responding to user input.
Fix this by properly initializing the pin to GPIO mode also when it is
used directly through irqchip.
Fixes: 303a3961afcd ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Reported-by: Daniel Drake <drake@endlessm.com> Reported-and-tested-by: Chris Chiu <chiu@endlessm.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Thu, 23 Nov 2017 10:01:49 +0000 (19:01 +0900)]
gpio: uniphier: fix mismatch between license text and MODULE_LICENSE
The comment block of this file indicates GPL-2.0 "only", while the
MODULE_LICENSE is GPL-2.0 "or later", as include/linux/module.h
describes as follows:
"GPL" [GNU Public License v2 or later]
"GPL v2" [GNU Public License v2]
I am the author of this driver, and my intention is GPL-2.0 "only".
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