Konrad Dybcio [Sat, 9 Jan 2021 16:29:59 +0000 (17:29 +0100)]
arm64: dts: qcom: msm8998: Disable some components by default
Some components (like PCIe) are not used on all devices and
with a certain firmware configuration they might end up triggering
a force reboot or a Synchronous Abort.
This commit brings no functional difference as the nodes are
enabled on devices which didn't disable them previously.
The BLSP2-connected interfaces started from 0 which is.. misleading
to say the least.. the clock names corresponding to these started
from 1, so let's align to that so as to reduce confusion.
* Move 35500 clock-frequency to kitakami (turns out it's a Sony specific)
* Add missing interfaces
* Fix the naming scheme
* Fix up pin assignments to make all BLSPs work
* Add DMA where previously omitted
Signed-off-by: Gustave Monce <gustave.monce@outlook.com> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210131013853.55810-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
RB5 has 3 PCIe ports exposed to connect PCIe client devices. PCIe0 is
connected to QCA6391 chipset and others are available on the HS3
expansion connector. Hence, enable all of them.
Add PCIe support for Qcom SM8250 SoC. This SoC has 3 PCIe Gen 3
instances based on Designware IP, out of which PCIe0 has 1 lane support
and the rest have 2 lane support.
Vinod Koul [Wed, 27 Jan 2021 12:30:54 +0000 (18:00 +0530)]
arm64: dts: qcom: Add basic devicetree support for SM8350-MTP board
Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC
MTP board. This enabled uart node and adds rpmh-regulators present for
this board.
Vincent Knecht [Sat, 30 Jan 2021 10:57:11 +0000 (11:57 +0100)]
arm64: dts: qcom: Add device tree for Alcatel Idol 3 (4.7")
The Alcatel Idol 3 (4.7") is a smartphone based on MSM8916.
Add a device tree with support for USB, eMMC, SD-Card, WiFi,
BT, power/volume buttons, vibrator and the following sensors:
magnetometer, accelerometer, gyroscope, ambient light+proximity
Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20210130105717.2628781-3-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Eric Biggers [Thu, 21 Jan 2021 09:01:39 +0000 (01:01 -0800)]
arm64: dts: qcom: sdm630: add ICE registers and clocks
Add the registers and clock for the Inline Crypto Engine (ICE) to the
device tree node for the sdhci-msm host controller on sdm630. This
allows sdhci-msm to support inline encryption on sdm630.
Dmitry Baryshkov [Tue, 19 Jan 2021 05:48:47 +0000 (08:48 +0300)]
arm64: dts: sm8250-mtp: add thermal zones using pmic's adc-tm5
Port thermal zones definitions from msm-4.19 tree. Enable and add
channel configuration to PMIC's ADC-TM definitions. Declare thermal
zones and respective trip points.
arm64: dts: pmi8998: Add the right interrupts for LAB/IBB SCP and OCP
In commit 208921bae696 ("arm64: dts: qcom: pmi8998: Add nodes for
LAB and IBB regulators") bindings for the lab/ibb regulators were
added to the pmi8998 dt, but the original committer has never
specified what the interrupts were for.
LAB and IBB regulators provide two interrupts, SC-ERR (short
circuit error) and VREG-OK but, in that commit, the regulators
were provided with two different types of interrupts;
specifically, IBB had the SC-ERR interrupt, while LAB had the
VREG-OK one, none of which were (luckily) used, since the driver
didn't actually use these at all.
Assuming that the original intention was to have the SC IRQ in
both LAB and IBB, as per the names appearing in documentation,
fix the SCP interrupt.
While at it, also add the OCP interrupt in order to be able to
enable the Over-Current Protection feature, if requested.
Robert Foss [Mon, 21 Dec 2020 10:09:55 +0000 (11:09 +0100)]
arm64: dts: qcom: sdm845-db845c: Fix reset-pin of ov8856 node
Switch reset pin of ov8856 node from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW,
this issue prevented the ov8856 from probing properly as it did not respon
to I2C messages.
Lower drive strength for microSD data and CMD pins from 16 to 10. This
fixes spurious card removal issues observed on some boards. Also this
change allows us to re-enable 1.8V support, which seems to work with
lowered drive strength.
arm64: dts: qcom: sc7180: Add labels for cpuN-thermal nodes
Add labels to the cpuN-thermal nodes to allow board files to use
a phandle instead replicating the node hierarchy when adjusting
certain properties.
Due to the 'sustainable-power' property CPU thermal zones are
more likely to need property updates than other SC7180 zones,
hence only labels for CPU zones are added for now.
Danny Lin [Tue, 12 Jan 2021 01:32:54 +0000 (17:32 -0800)]
arm64: dts: qcom: sm8250: Add CPU capacities and energy model
Power and performance measurements were made using my freqbench [1]
benchmark coordinator, which isolates, offlines, and disables the timer
tick on test CPUs to maximize accuracy. It uses EEMBC CoreMark [2] as
the workload and measures power usage using the PM8150B PMIC's fuel
gauge.
The energy model dynamic-power-coefficient values were calculated with
DPC = µW / MHz / V^2
for each OPP, and averaged across all OPPs within each cluster for the
final coefficient. Voltages were obtained from the qcom-cpufreq-hw
driver that reads voltages from the OSM LUT programmed into the SoC.
Normalized DMIPS/MHz capacity scale values for each CPU were calculated
from CoreMarks/MHz (CoreMark iterations per second per MHz), which
serves the same purpose. For each CPU, the final capacity-dmips-mhz
value is the C/MHz value of its maximum frequency normalized to
SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system.
A Xiaomi Redmi K30S Ultra device running a downstream Qualcomm 4.19
kernel was used for benchmarking to ensure proper frequency scaling and
other low-level controls.
Raw benchmark results can be found in the freqbench repository [3].
Below is a human-readable summary:
Frequency domains: cpu1 cpu4 cpu7
Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7
Baseline power usage: 1223 mW
Danny Lin [Tue, 12 Jan 2021 01:32:53 +0000 (17:32 -0800)]
arm64: dts: qcom: sm8250: Define CPU topology
sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.
When the BMC150 accelerometer/magnetometer was added to the device tree,
the sensors were working without specifying any regulator supplies,
likely because the regulators were on by default and then never turned off.
For some reason, this is no longer the case for pm8916_l17, which prevents
the sensors from working in some cases.
Now that the bmc150_accel/bmc150_magn drivers can enable necessary
regulators, declare the necessary regulator supplies to make the sensors
work again.
arm64: dts: sdm850: Add OPP tables for 2.84 and 2.96GHz
Running cpufreq-hw driver on Lenovo Yoga C630 laptop, the following
warning messages will be seen.
[ 3.415340] cpu cpu4: Voltage update failed freq=2841600
[ 3.418755] cpu cpu4: failed to update OPP for freq=2841600
[ 3.422949] cpu cpu4: Voltage update failed freq=2956800
[ 3.427086] cpu cpu4: failed to update OPP for freq=2956800
This is because the cpufreq-hw lookup table of SDM850 provides these two
set-points, but they are missing from OPP table in DT. Let's create
sdm850.dtsi to add the OPP for them, so that the warning will be gone.
Danny Lin [Tue, 5 Jan 2021 20:10:00 +0000 (12:10 -0800)]
arm64: dts: qcom: sm8150: Add support for deep CPU cluster idle
This commit adds support for deep idling of the entire unified DynamIQ
CPU cluster on sm8150. In this idle state, the LLCC (Last-Level Cache
Controller) is powered off and the AOP (Always-On Processor) enters a
low-power sleep state.
I'm not sure what the per-CPU 0x400000f4 idle state previously
contributed by Qualcomm as the "cluster sleep" state is, but the
downstream kernel has no such state. The real deep cluster idle state
is 0x41000c244, composed of:
arm64: dts: qcom: Clean up sc7180-trogdor voltage rails
For a bunch of rails we really don't do anything with them in Linux.
These are things like modem voltage rails that the modem manages these
itself and core rails (like IO rails) that are setup to just
automagically do the right thing by the firmware.
Let's stop even listing those rails in our device tree.
The net result of this is that some of these rails might be able to go
down to a lower voltage or perhaps transition to LPM (low power mode)
sometimes.
Here's a list of what we're doing and why:
* L1A - only goes to SoC and doesn't seem associated with any
particular peripheral. Kernel isn't doing anything with
this. Removing from dts. NET IMPACT: rail might drop from 1.2V to
1.178V and switch to LPM in some cases depending on firmware.
* L2A - only goes to SoC and doesn't seem associated with any
particular peripheral. Kernel isn't doing anything with
this. Removing from dts. NET IMPACT: rail might switch to LPM in
some cases depending on firmware.
* L3A - only goes to SoC and doesn't seem associated with any
particular peripheral. Kernel isn't doing anything with
this. Removing from dts. NET IMPACT: rail might switch to LPM in
some cases depending on firmware.
* L5A - seems to be totally unused as far as I can tell and doesn't
even come off QSIP. Removing from dts.
* L6A - only goes to SoC and doesn't seem associated with any
particular peripheral (I think?). Kernel isn't doing anything with
this. Removing from dts. NET IMPACT: rail might switch to LPM in
some cases depending on firmware.
* L16A - Looks like this is only used for internal RF stuff. Removing
from dts. NET IMPACT: rail might switch to LPM in some cases
depending on firmware.
* L1C - Just goes to WiFi / Bluetooth. Trust how IDP has this set and
put this back at 1.616V min.
* L4C - This goes out to the eSIM among other places. This looks like
it's intended to be for SIM card and modem manages. NET IMPACT:
rail might switch to LPM in some cases depending on firmware.
* L5C - This goes to the physical SIM. This looks like it's intended
to be for SIM card and modem manages. NET IMPACT: rail might drop
from 1.8V to 1.648V and switch to LPM in some cases depending on
firmware.
NOTE: in general for anything which is supposed to be managed by Linux
I still left it all forced to HPM since I'm not 100% sure that all the
needed calls to regulator_set_load() are in place and HPM is safer.
Switching more things to LPM can happen in a future patch.
ALSO NOTE: Power measurements showed no measurable difference after
applying this patch, so perhaps it should be viewed more as a cleanup
than any power savings.
Unlike most MSM8916 boards, samsung-a5u uses WCN3660B instead of
WCN3620 to support the 5 GHz band additionally.
WCN3660B has similar requirements as WCN3620, but it needs the XO
clock to run at 48 MHz instead of 19.2 MHz. So far it was possible
to describe that configuration using the qcom,wcn3680 compatible.
However, as of commit 8490987bdb9a ("wcn36xx: Hook and identify RF_IRIS_WCN3680"),
the wcn36xx driver will now use the qcom,wcn3680 compatible
to enable functionality specific to WCN3680. In particular,
WCN3680 supports 802.11ac, which is not available in WCN3660B.
Use the new qcom,wcn3660b compatible to describe the chip properly.
Danny Lin [Mon, 21 Dec 2020 00:29:07 +0000 (16:29 -0800)]
arm64: dts: qcom: sm8150: Add CPU capacities and energy model
Power and performance measurements were made using my freqbench [1]
benchmark coordinator, which isolates, offlines, and disables the timer
tick on test CPUs to maximize accuracy. It uses EEMBC CoreMark [2] as
the workload and measures power usage using the PM8150B PMIC's fuel
gauge.
The energy model dynamic-power-coefficient values were calculated with
DPC = µW / MHz / V^2
for each OPP, and averaged across all OPPs within each cluster for the
final coefficient. Voltages were obtained from the qcom-cpufreq-hw
driver that reads voltages from the OSM LUT programmed into the SoC.
Normalized DMIPS/MHz capacity scale values for each CPU were calculated
from CoreMarks/MHz (CoreMark iterations per second per MHz), which
serves the same purpose. For each CPU, the final capacity-dmips-mhz
value is the C/MHz value of its maximum frequency normalized to
SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system.
An Asus ZenFone 6 device running a downstream Qualcomm 4.14 kernel
(LA.UM.8.1.r1-15600-sm8150.0) was used for benchmarks to ensure proper
frequency scaling and other low-level controls.
Raw benchmark results can be found in the freqbench repository [3].
Below is a human-readable summary:
Frequency domains: cpu1 cpu4 cpu7
Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7
Baseline power usage: 1400 mW
Danny Lin [Mon, 21 Dec 2020 00:29:06 +0000 (16:29 -0800)]
arm64: dts: qcom: sm8150: Add PSCI idle states
Like other Qualcomm SoCs, sm8150 exposes CPU and cluster idle states
through PSCI. Define the idle states to save power when the CPU is not
in active use.
These idle states, latency, and residency values match the downstream
4.14 kernel from Qualcomm as of LA.UM.8.1.r1-15600-sm8150.0.
It's worth noting that the CPU has an additional C3 power collapse idle
state between WFI and rail power collapse (with PSCI mode 0x40000003),
but it is not officially used in downstream kernels due to "thermal
throttling issues."
Danny Lin [Mon, 21 Dec 2020 00:29:05 +0000 (16:29 -0800)]
arm64: dts: qcom: sm8150: Define CPU topology
sm8150 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.
Stephen Boyd [Tue, 15 Dec 2020 02:00:04 +0000 (18:00 -0800)]
arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_det
We shouldn't put any pinconf here in case someone decides to invert this
HPD signal or remove an external pull-down. It's better to leave that to
the board pinconf nodes, so drop it here.
Reviewed-by: Douglas Anderson <dianders@chromium.org> Reported-by: Douglas Anderson <dianders@chromium.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Fixes: 681a607ad21a ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20201215020004.731239-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
arm64: dts: qcom: Fix SD card vqmmc max voltage on sc7180-trogdor
It never makes sense to set the IO voltage of the SD card (vqmmc) to a
voltage that's higher than the voltage of the card's main power supply
(vmmc). The card's main voltage is 2.952V on trogdor, so let's set
the max for the IO voltage to the same.
NOTE: On Linux, this is pretty much a no-op currently. Linux already
makes an effort to match vqmmc with vmmc when running at "3.3" signal
voltage, so both before and after this change we end up running vqmmc
at 2.904V when talking to non-UHS cards. It still seems cleaner to
make it a little more correct, though.
Also note: as per above, on Linux right now we end up running vqmmc as
2.904V even though vmmc is 2.952V. This isn't super ideal but
shouldn't really hurt.
Dmitry Baryshkov [Fri, 27 Nov 2020 09:26:46 +0000 (12:26 +0300)]
arm64: dts: sm8250-mtp: enable USB host nodes
Enable both USB host controller, hsphy and qmpphy nodes on sm8250. Add
missing pm8150 ldo18 definition (used by USB qmp phys). Both controllers
are locked to host mode: dual role on first controller is not enabled.
arm64: dts: qcom: sm8250: Add support for LLCC block
Add support for Last Level Cache Controller (LLCC) in SM8250 SoC.
This LLCC is used to provide common cache memory pool for the cores in
the SM8250 SoC thereby minimizing the percore caches.
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