Different issues with the same fix, so justing adding
Wa_1409142259, Wa_1409252684, Wa_1409217633, Wa_1409207793,
Wa_1409178076 and 1408979724 to the comment so other devs can check if
this Was were implemetend with a simple grep.
Anusha Srivatsa [Thu, 27 Feb 2020 22:00:54 +0000 (14:00 -0800)]
drm/i915/tgl: Extend Wa_1606931601 for all steppings
According to BSpec. Wa_1606931601 applies for all TGL steppings.
This patch moves the WA implementation out of A0 only block of
rcs_engine_wa_init().
The WA is has also been referred to by an alternate name
Wa_1607090982.
Bspec: 46045, 52890
Fixes: 3873fd1a43c7 ("drm/i915: Use engine wa list for Wa_1607090982") Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-4-jose.souza@intel.com
Matt Atwood [Thu, 27 Feb 2020 22:00:53 +0000 (14:00 -0800)]
drm/i915/tgl: Add Wa_1409085225, Wa_14010229206
Disable Push Constant buffer addition for TGL.
v2: typos, add additional Wa reference
v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit
message.
Bspec: 52890 Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-3-jose.souza@intel.com
Imre Deak [Fri, 28 Feb 2020 15:33:28 +0000 (17:33 +0200)]
drm/i915: Unify the DPLL ref clock frequency tracking
All platforms using the shared DPLL framework use 3 reference clocks for
their DPLLs: SSC, non-SSC and DSI. For a more unified way across
platforms store the frequency of these ref clocks as part of the DPLL
global state. This also allows us to keep the HW access reading out the
ref clock value separate from the DPLL frequency calculation that
depends on the ref clock.
For now add only the SSC and non-SSC ref clocks, as the pre-ICL DSI code
has its own logic for calculating DPLL parameters instead of the shared
DPLL framework.
v2:
- Apply the ICL combo PHY PLL ref_clock/2 adjustment during the
frequency->PLL param conversion direction as well. (CI shards)
- s/kHZ/kHz/ (Ville)
Imre Deak [Wed, 26 Feb 2020 20:34:50 +0000 (22:34 +0200)]
drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
The types of PLLs used for HDMI/DP on HSW are WRPLL/LCPLL accordingly,
so use these names to align better with the rest of WRPLL/LCPLL function
names elsewhere.
Imre Deak [Wed, 26 Feb 2020 20:34:49 +0000 (22:34 +0200)]
drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
For clarity keep the SKL DPLL ref clock in a variable instead of
open-coding it. Store the value in kHZ units as done on other platforms.
This allows us in a later patch to keep track of the DPLL ref clock in a
more unified way across all platforms.
Imre Deak [Wed, 26 Feb 2020 20:34:48 +0000 (22:34 +0200)]
drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
Move all the DPLL params->DPLL frequency conversion functions to
intel_dpll_mgr.c where the corresponding inverse conversions are.
The GEN11+ TBT PLL outputs multiple frequencies and for selecting the
one in use we need to check the DDI CLK mux. As part of the DDI clock
logic this selection is kept in intel_ddi.c.
Imre Deak [Wed, 26 Feb 2020 20:34:45 +0000 (22:34 +0200)]
drm/i915: Keep the global DPLL state in a DPLL specific struct
For clarity add a new DPLL specific struct to the i915 device struct and
move all DPLL fields into it. Accordingly remove the dpll_ prefixes, as
the new struct already provides the required namespacing.
drm/i915: Use intel_plane_data_rate for min_cdclk calculation
There seems to be a bit of confusing redundancy in a way, how
plane data rate/min cdclk are calculated.
In fact both min cdclk, pixel rate and plane data rate are all
part of the same formula as per BSpec.
However currently we have intel_plane_data_rate, which is used
to calculate plane data rate and which is also used in bandwidth
calculations. However for calculating min_cdclk we have another
piece of code, doing almost same calculation, but a bit differently
and in a different place. However as both are actually part of same
formula, probably would be wise to use plane data rate calculations
as a basis anyway, thus avoiding code duplication and possible bugs
related to this.
Another thing is that I've noticed that during min_cdclk calculations
we account for plane scaling, while for plane data rate, we don't.
crtc->pixel_rate seems to account only for pipe ratio, however it is
clearly stated in BSpec that plane data rate also need to account
plane ratio as well.
So what this commit does is:
- Adds a plane ratio calculation to intel_plane_data_rate
- Removes redundant calculations from skl_plane_min_cdclk which is
used for gen9+ and now uses intel_plane_data_rate as a basis from
there as well.
v2: - Don't use 64 division if not needed(Ville Syrjälä)
- Now use intel_plane_pixel_rate as a basis for calculations both
at intel_plane_data_rate and skl_plane_min_cdclk(Ville Syrjälä)
v3: - Again fix the division macro
- Fix plane_pixel_rate to pixel_rate at intel_plane_pixel_rate
callsites
v4: - Renamed skl_plane_ratio function back(Ville Syrjälä)
v5: - Don't precalculate plane pixel rate for invisible plane,
check for visibility first, as in invisible case it will
have dst_w and dst_h equal to zero, causing divide error.
v6: - Removed useless warn in intel_plane_pixel_rate(Ville Syrjälä)
- Fixed alignment in intel_plane_data_rate(Ville Syrjälä)
- Changed pixel_rate type to be unsigned int in
skl_plane_min_cdclk(Ville Syrjälä)
Ville Syrjälä [Tue, 25 Feb 2020 17:11:09 +0000 (19:11 +0200)]
drm/i915: Use a sentinel to terminate the dbuf slice arrays
Make life a bit simpler by sticking a sentinel at the end of
the dbuf slice arrays. This way we don't need to pass in the
size. Also unify the types (u8 vs. u32) for active_pipes.
Ville Syrjälä [Tue, 25 Feb 2020 17:11:08 +0000 (19:11 +0200)]
drm/i915: Add missing commas to dbuf tables
The preferred style is to sprinkle commas after each array and
structure initialization, whether or not it happens to be the
last element/member (only exception being sentinel entries which
never have anything after them). This leads to much prettier
diffs if/when new elements/members get added to the end of the
initialization. We're not bound by some ancient silly mandate
to omit the final comma.
Supposedly both src coordinates have to even when doing 90/270
degree rotation with RGB565. This is definitely true for the
X coordinate (we just get a black screen when it is odd). My
experiments didn't show any misbehaviour with an odd
Y coordinate, but let's trust the spec and reject that one
as well.
v2: Ignore ccs hsub/vsub
v3: Clarify the CCS special (Maarten)
Deal with tgl+ CCS modifiers where we
do need to look at hsub/vsub
Hans de Goede [Fri, 28 Feb 2020 11:41:10 +0000 (12:41 +0100)]
drm/i915/dp: Use BDB_GENERAL_FEATURES VBT block info for builtin panel-orientation
Some devices with a builtin panel have the panel mounted upside down,
this is indicated by the rotate_180 bit in the BDB_GENERAL_FEATURES VBT
block.
We store this info in dev_priv->vbt.orientation, use this to set the
connector's orientation property so that fbcon and userspace will show
the image the right way up on devices with an upside-down mounted panel.
This fixes the image being upside-down on a Teclast X89 tablet.
Hans de Goede [Fri, 28 Feb 2020 11:41:09 +0000 (12:41 +0100)]
drm/i915/dsi: Remove readback of panel orientation on BYT / CHT
Commit 82daca297506 ("drm/i915: Add "panel orientation" property to the
panel connector, v6.") uses hardware state readback to determine if the
GOP is rotating the image by 180 degrees to compensate for upside-down
mounted panels.
When I wrote that commit I tried to find the VBT bits the GOP used to
decide to rotate the image, but I could not find them. Back then I only
looked at the rotation bits in struct mipi_config and these read 0 on
the 1 BYT device I have with an upside-down mounted panel
(a GP-electronic T701 tablet). While working on a similar problem on a
BYT device with an eDP panel I noticed that the new
intel_dsi_get_panel_orientation() helper which gets used on newer
SoCs (Apollo-Lake, etc.) checks the rotate_180 bit in the
BDB_GENERAL_FEATURES VBT block.
I've checked and this bit indeed is set on the GP-electronic T701 tablet,
so using the generic intel_dsi_get_panel_orientation() helper there does
the right thing without needing any extra readback of hw state.
This commit removes the special handling of the panel orientation for
DSI panels on BYT/CHT devices, bringing the handling in line with the
handling of DSI panels on other devices.
Jani Nikula [Thu, 27 Feb 2020 14:53:59 +0000 (16:53 +0200)]
drm/i915/dram: hide the dram structs better
Finish the job started in d28ae3b28187 ("drm/i915: split out
intel_dram.[ch] from i915_drv.c") by moving struct dram_dimm_info and
dram_channel_info inside intel_dram.c, the only user of the structs.
Jani Nikula [Thu, 27 Feb 2020 16:12:53 +0000 (18:12 +0200)]
drm/i915/crc: move pipe_crc from drm_i915_private to intel_crtc
Having an array pipe_crc[I915_MAX_PIPES] in struct drm_i915_private
should be an obvious clue this should be located in struct intel_crtc
instead. Make it so.
As a side-effect, fix some errors in indexing pipe_crc with both pipe
and crtc index. And, of course, reduce the size of i915_drv.h.
Chris Wilson [Fri, 28 Feb 2020 13:17:16 +0000 (13:17 +0000)]
drm/i915/gt: Expose heartbeat interval via sysfs
We monitor the health of the system via periodic heartbeat pulses. The
pulses also provide the opportunity to perform garbage collection.
However, we interpret an incomplete pulse (a missed heartbeat) as an
indication that the system is no longer responsive, i.e. hung, and
perform an engine or full GPU reset. Given that the preemption
granularity can be very coarse on a system, we let the sysadmin override
our legacy timeouts which were "optimised" for desktop applications.
The heartbeat interval can be adjusted per-engine using,
Chris Wilson [Fri, 28 Feb 2020 13:17:15 +0000 (13:17 +0000)]
drm/i915/gt: Expose preempt reset timeout via sysfs
After initialising a preemption request, we give the current resident a
small amount of time to vacate the GPU. The preemption request is for a
higher priority context and should be immediate to maintain high
quality of service (and avoid priority inversion). However, the
preemption granularity of the GPU can be quite coarse and so we need a
compromise.
The preempt timeout can be adjusted per-engine using,
Chris Wilson [Fri, 28 Feb 2020 13:17:14 +0000 (13:17 +0000)]
drm/i915/gt: Expose reset stop timeout via sysfs
When we allow ourselves to sleep before a GPU reset after disabling
submission, even for a few milliseconds, gives an innocent context the
opportunity to clear the GPU before the reset occurs. However, how long
to sleep depends on the typical non-preemptible duration (a similar
problem to determining the ideal preempt-reset timeout or even the
heartbeat interval). As this seems of a hard policy decision, punt it to
userspace.
Chris Wilson [Fri, 28 Feb 2020 13:17:13 +0000 (13:17 +0000)]
drm/i915/gt: Expose busywait duration to sysfs
We busywait on an inflight request (one that is currently executing on
HW, and so might complete quickly) prior to setting up an interrupt and
sleeping. The trade off is that we keep an expensive CPU core busy in
order to avoid wake up latency: where that trade off should lie is best
left to the sysadmin.
Chris Wilson [Fri, 28 Feb 2020 13:17:12 +0000 (13:17 +0000)]
drm/i915/gt: Expose timeslice duration to sysfs
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to userspace semaphores.
The timeslicing mechanism can be compiled out with
Chris Wilson [Fri, 28 Feb 2020 13:17:11 +0000 (13:17 +0000)]
drm/i915/gt: Expose engine->mmio_base via sysfs
Use the per-engine sysfs directory to let userspace discover the
mmio_base of each engine. Prior to recent generations, the user
accessible registers on each engine are at a fixed offset relative to
each engine -- but require absolute addressing. As the absolute address
depends on the actual physical engine, this is not always possible to
determine from userspace (for example icl may expose vcs1 or vcs2 as the
second vcs engine). Make this easy for userspace to discover by
providing the mmio_base in sysfs.
Chris Wilson [Fri, 28 Feb 2020 13:17:10 +0000 (13:17 +0000)]
drm/i915/gt: Expose engine properties via sysfs
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure. Later we will add writeable sysadmin properties such
as per-engine timeout controls.
An example tree of the engine properties on Braswell:
/sys/class/drm/card0
└── engine
├── bcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── rcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── vcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
└── vecs0
├── capabilities
├── class
├── instance
├── known_capabilities
└── name
v2: Include stringified capabilities
v3: Include all known capabilities for futureproofing.
v4: Combine the two caps loops into one
v5: Hide underneath Kconfig.unstable for wider discussion
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Tested-by: Steve Carbonari <steven.carbonari@intel.com> Reviewed-by: Steve Carbonari <steven.carbonari@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200228131716.3243616-1-chris@chris-wilson.co.uk
Dan Carpenter [Fri, 28 Feb 2020 14:14:13 +0000 (17:14 +0300)]
drm/i915/selftests: Fix return in assert_mmap_offset()
The assert_mmap_offset() returns type bool so if we return an error
pointer that is "return true;" or success. If we have an error, then
we should return false.
Chris Wilson [Thu, 27 Feb 2020 08:57:12 +0000 (08:57 +0000)]
drm/i915/gt: Reset queue_priority_hint after wedging
An odd and highly unlikely path caught us out. On delayed submission
(due to an asynchronous reset handler), we poked the priority_hint and
kicked the tasklet. However, we had already marked the device as wedged
and swapped out the tasklet for a no-op. The result was that we never
cleared the priority hint and became upset when we later checked.
Chris Wilson [Fri, 28 Feb 2020 08:23:24 +0000 (08:23 +0000)]
drm/i915/selftests: Wait for the context switch
As we require a context switch to ensure that the current context is
switched out and saved to memory, perform an explicit switch to the
kernel context and wait for it.
Chris Wilson [Thu, 27 Feb 2020 08:57:06 +0000 (08:57 +0000)]
drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
The engine->kernel_context is a special case for request emission. Since
it is used as the barrier within the engine's wakeref, we must acquire the
wakeref before submitting a request to the kernel_context.
Chris Wilson [Thu, 27 Feb 2020 08:57:05 +0000 (08:57 +0000)]
drm/i915/perf: Mark up the racy use of perf->exclusive_stream
Inside the general i915_oa_init_reg_state() we avoid using the
perf->mutex. However, we rely on perf->exclusive_stream being valid to
access at that point, and for that we have to control the race with
disabling perf. This relies on the disabling being a heavy barrier that
inspects all active contexts, after marking the perf->exclusive_stream
as not available. This should ensure that there are no more concurrent
accesses to the perf->exclusive_stream as we destroy it.
Mark up the races around the perf->exclusive_stream so that they stand
out much more. (And hopefully we will be running kcsan to start
validating that the only races we have are carefully controlled.)
Anshuman Gupta [Wed, 26 Feb 2020 16:35:17 +0000 (22:05 +0530)]
drm/i915: Fix wrongly populated plane possible_crtcs bit mask
As a disabled pipe in pipe_mask is not having a valid intel crtc,
driver wrongly populates the possible_crtcs mask while initializing
the plane for a CRTC. Fixing up the plane possible_crtcs mask.
changes since RFC:
- Simplify the possible_crtcs initialization. [Ville]
v2:
- Removed the unnecessary stack garbage possible_crtcs to
drm_universal_plane_init. [Ville]
v3:
- Combine the intel_crtc assignment and declaration. [Ville]
v4:
- Fix possible_crtcs abused bits from
intel_{primary,curosr,sprite}_plane_create(). [Ville]
Chris Wilson [Thu, 27 Feb 2020 08:57:14 +0000 (08:57 +0000)]
drm/i915: Protect i915_request_await_start from early waits
We need to be extremely careful inside i915_request_await_start() as it
needs to walk the list of requests in the foreign timeline with very
little protection. As we hold our own timeline mutex, we can not nest
inside the signaler's timeline mutex, so all that remains is our RCU
protection. However, to be safe we need to tell the compiler that we may
be traversing the list only under RCU protection, and furthermore we
need to start declaring requests as elements of the timeline from their
construction.
Chris Wilson [Thu, 27 Feb 2020 08:57:16 +0000 (08:57 +0000)]
drm/i915/selftests: Check recovery from corrupted LRC
Check that we can recover if the LRC is totally corrupted. Based on a
very simple theory that anything that can be adjusted via the context
(i.e. on behalf of the user), should be under the purview of the
per-engine-reset.
Chris Wilson [Thu, 27 Feb 2020 08:57:15 +0000 (08:57 +0000)]
drm/i915/selftests: Verify LRC isolation
Record the LRC registers before/after a preemption event to ensure that
the first context sees nothing from the second client; at least in the
normal per-context register state.
Chris Wilson [Thu, 27 Feb 2020 08:57:13 +0000 (08:57 +0000)]
drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
Pull the final atomic_dec of vm->open (marking the vm as closed)
underneath the same vm->mutex as used to close it. This is required to
correctly serialise with attempting to reuse the vma as the vm is closed
by a second thread.
Chris Wilson [Thu, 27 Feb 2020 20:47:27 +0000 (20:47 +0000)]
drm/i915/gt: Check engine-is-awake on reset later
As we drop the engine-pm on retiring, that may happen while there are
still CS events in the buffer. As such we cannot assert the engine is
still active on reset, until we know that the current request is still
in flight.
Chris Wilson [Thu, 27 Feb 2020 08:57:04 +0000 (08:57 +0000)]
drm/i915: Skip barriers inside waits
Attaching to the i915_active barrier is a two stage process, and a flush
is only effective when the barrier is activation. Thus it is possible
for us to see a barrier, and attempt to flush, only for our flush to
have no effect. As such, before attempting to activate signaling on the
fence we need to double check it is a fence!
On TGL, bits 2-4 in the GGTT PTE are not ignored anymore and are
instead used for some extra VT-d capabilities. We don't (yet?) have
support for those capabilities, but, given that we shared the pte_encode
function betweed GGTT and PPGTT, we still set those bits to the PPGTT
PPAT values. The DMA engine gets very confused when those bits are
set while the iommu is enabled, leading to errors. E.g. when loading
the GuC we get:
To fix this, just have dedicated gen8_pte_encode function per type of
gtt. Also, explicitly set vm->pte_encode for gen8_ppgtt, even if we
don't use it, to make sure we don't accidentally assign it to the GGTT
one, like we do for gen6_ppgtt, in case we need it in the future.
Reported-by: "Sodhi, Vunny" <vunny.sodhi@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200226185657.26445-1-daniele.ceraolospurio@intel.com
Lucas De Marchi [Mon, 24 Feb 2020 19:12:58 +0000 (11:12 -0800)]
drm/i915/tgl: Add Wa_1608008084
Wa_1608008084 is an additional WA that applies to writes on FF_MODE2
register. We can't read it back either from CPU or GPU. Since the other
bits should be 0, recommendation to handle Wa_1604555607 is to actually
just write the timer value.
Do a write only and don't try to read it, neither before or after
the WA is applied.
Ville Syrjälä [Wed, 26 Feb 2020 16:30:54 +0000 (18:30 +0200)]
drm/i915: Set up PIPE_MISC truncate bit on tgl+
Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to
PIPE_MISC on tgl. Frob the new location.
Bspec does still document the old bits as well, so I left the code
for them as is until we get clarification from the hw folks on
whether the old bits still do something useful.
Lucas De Marchi [Fri, 8 Mar 2019 23:23:21 +0000 (15:23 -0800)]
drm/i915: remove ICP_PP_CONTROL
This register was placed in the middle of the PP_STATUS definition
instead of together with the PP_CONTROL where it should. Since it's not
used and there are no current plans to use it, just remove the
definition.
Jani Nikula [Tue, 25 Feb 2020 11:15:09 +0000 (13:15 +0200)]
drm/i915/drv: use intel_uncore_write() for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace the sole remaining I915_WRITE() in i915_drv.c with
intel_uncore_write(), although it might be better to keep the entire
file void of direct register access.
Jani Nikula [Tue, 25 Feb 2020 11:15:08 +0000 (13:15 +0200)]
drm/i915/dram: use intel_uncore_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding uncore register accessors
intel_uncore_read(), intel_uncore_write(), intel_uncore_posting_read(),
intel_uncore_read_fw(), and intel_uncore_write_fw().
Jani Nikula [Tue, 25 Feb 2020 11:15:07 +0000 (13:15 +0200)]
drm/i915: split out intel_dram.[ch] from i915_drv.c
The DRAM related routines are pretty isolated from the rest of the
i915_drv.c, split it out to a separate file. Put the eDRAM stuff in the
same bag, and rename the visible functions to have intel_dram_
prefix. Do some benign whitespace fixes and dev_priv -> i915 conversions
while at it.
Matt Atwood [Mon, 24 Feb 2020 22:36:51 +0000 (14:36 -0800)]
drm/i915/tgl: Add Wa_1606054188:tgl
On Tiger Lake we do not support source keying in the pixel formats P010,
P012, P016.
v2: Move WA to end of function. Create helper function for format
check. Less verbose debugging messaging.
v3: whitespace
v4(MattR):
- Actually return EINVAL to reject this combination.
- Pass format parameter as u32.
- Make test TGL-specific for now.
- Switch to per-device logging.
- Shorten/simplify comment.
Bspec: 52890 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200224223651.3801646-1-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Rodrigo Vivi [Wed, 26 Feb 2020 22:58:14 +0000 (14:58 -0800)]
Merge tag 'gvt-next-2020-02-26' of https://github.com/intel/gvt-linux into drm-intel-next-queued
gvt-next-2020-02-26
- Enable VFIO edid for all platform (Zhenyu)
- Code cleanup for attr group and unused vblank complete (Zhenyu, Julian)
- Make gvt oblivious of kvmgt data structures (Julian)
- Make WARN* drm specific (Pankaj)
Anshuman Gupta [Mon, 24 Feb 2020 12:40:02 +0000 (18:10 +0530)]
drm/i915: Get first crtc instead of PIPE_A crtc
intel_plane_fb_max_stride should return the max stride of
primary plane for first available pipe in intel device info
pipe_mask.
Similarly glk_force_audio_cdclk() should also use the first
available CRTC instead of pipe 'A' crtc to force the cdclk
changes.
changes since RFC:
- Introduced a helper to get first intel_crtc intel_get_first_crtc. [Ville]
v1:
- Used intel_get_first_crtc() instead of PIPE_A crtc in
glk_force_audio_cdclk(). [Ville]
Anshuman Gupta [Mon, 24 Feb 2020 12:40:00 +0000 (18:10 +0530)]
drm/i915: Fix broken transcoder err state
Skip the transcoder whose pipe is disabled while
initializing transcoder error state in 3 non-contiguous
display pipe system.
v2:
- Don't skip EDP_TRANSCODER error state. [Ville]
- Use a helper has_transcoder(). [Ville]
v3:
- Removed DSI transcoder case from has_transcoder(),
and few other cosmetic changes. [Ville]
Anshuman Gupta [Mon, 24 Feb 2020 12:39:59 +0000 (18:09 +0530)]
drm/i915: Remove (pipe == crtc->index) assumption
we can't have (pipe == crtc->index) assumption in
driver in order to support 3 non-contiguous
display pipe system.
FIXME: Remove the WARN_ON(drm_crtc_index(&crtc->base) != crtc->pipe)
when we will fix all such assumption.
changes since RFC:
- Added again removed (pipe == crtc->index) WARN_ON.
- Pass drm_crtc_index instead of intel pipe in order to
call drm_handle_vblank().
v2:
- Used drm_crtc_handle_vblank()/drm_crtc_wait_one_vblank()
instead of drm_handle_vblank/drm_wait_one_vblank(). [Jani]
- Introduced intel_handle_vblank() helper to avoid sprinkle
of intel_crtc across irq_handlers. [Ville]
v3:
- Moved intel_handle_vblank() from header to i915_irq.c. [Ville]
Anshuman Gupta [Mon, 24 Feb 2020 12:39:58 +0000 (18:09 +0530)]
drm/i915: Iterate over pipes and skip the disabled one
It should not be assumed that a disabled display pipe will be
always last the pipe.
for_each_pipe() should iterate over I915_MAX_PIPES and check
for the disabled pipe and skip that pipe so that it should not
initialize the intel crtc for any disabled pipes.
Due to changes in for_each_pipe() macro, it requires to handle
the below compilation error.
"suggest explicit braces to avoid ambiguous ‘else’
[-Werror=dangling-else]"
Jani Nikula [Mon, 24 Feb 2020 12:08:28 +0000 (14:08 +0200)]
drm/i915: split intel_modeset_init() to pre/post irq install
Split inte_modeset_init() to parts before and after irq install, to
facilitate further cleanup. The error paths are a mess, otherwise no
functional changes.
Jani Nikula [Mon, 24 Feb 2020 11:33:12 +0000 (13:33 +0200)]
drm/i915: stop assigning drm->dev_private pointer
We no longer need or use it as we subclass struct drm_device in our
struct drm_i915_private, and can always use to_i915() to get at
i915. Stop assigning the pointer to catch anyone trying to add new users
for ->dev_private.
Chris Wilson [Tue, 25 Feb 2020 19:22:06 +0000 (19:22 +0000)]
drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Rodrigo Vivi [Tue, 25 Feb 2020 17:29:58 +0000 (09:29 -0800)]
Merge drm/drm-next into drm-intel-next-queued
Some DSI and VBT pending patches from Hans will apply
cleanly and with less ugly conflicts if they are rebuilt
on top of other patches that recently landed on drm-next.
Reference: https://patchwork.freedesktop.org/series/70952/ Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com
Tina Zhang [Tue, 25 Feb 2020 05:35:26 +0000 (13:35 +0800)]
drm/i915/gvt: Fix drm_WARN issue where vgpu ptr is unavailable
When vgpu ptr is unavailable, the drm_WARN* can hang the whole system
due to the drm pointer is NULL. This patch fixes this issue by using
WARN directly which won't care about the drm pointer.
drm/i915/psr: Force PSR probe only after full initialization
Commit 60c6a14b489b ("drm/i915/display: Force the state compute phase
once to enable PSR") was forcing the state compute too earlier
causing errors because not everything was initialized, so here
moving to the end of i915_driver_modeset_probe() when the display is
all initialized.
Also fixing the place where it disarm the force probe as during the
atomic check phase errors could happen like the ones due locking and
it would cause PSR to never be enabled if that happens.
Leaving the disarm to the atomic commit phase, intel_psr_enable() or
intel_psr_update() will be called even if the current state do not
allow PSR to be enabled.
v2: Check if intel_dp is null in intel_psr_force_mode_changed_set()
v3: Check intel_dp before get dev_priv
v4:
- renamed intel_psr_force_mode_changed_set() to
intel_psr_set_force_mode_changed()
- removed the set parameter from intel_psr_set_force_mode_changed()
- not calling intel_psr_set_force_mode_changed() from
intel_psr_enable/update(), directly setting it after the same checks
that intel_psr_set_force_mode_changed() does
- moved intel_psr_set_force_mode_changed() arm call to
i915_driver_modeset_probe() as it is a better for a PSR call, all the
functions calls happening between the old and the new function call
will cause issue
Fixes: 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable PSR") Closes: https://gitlab.freedesktop.org/drm/intel/issues/1151 Tested-by: Ross Zwisler <zwisler@google.com> Reported-by: Ross Zwisler <zwisler@google.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200221212635.11614-1-jose.souza@intel.com
Ville Syrjälä [Fri, 21 Feb 2020 15:43:10 +0000 (17:43 +0200)]
drm/i915: Correctly terminate connector iteration
One should use drm_connector_list_iter_end() rather than
drm_connector_list_iter_begin() to terminate the connector
iteration.
Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1278 Fixes: e24bcd34c1dd ("drm/i915/dp: Add all tiled and port sync conns to modeset") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200221154310.14858-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Jani Nikula [Fri, 21 Feb 2020 10:54:14 +0000 (12:54 +0200)]
drm/i915: fix header test with GCOV
$(CC) with $(CFLAGS_GCOV) assumes the output filename with .gcno suffix
appended is writable. This is not the case when the output filename is
/dev/null:
Chris Wilson [Sun, 23 Feb 2020 17:37:46 +0000 (17:37 +0000)]
drm/i915/display: Fix inverted WARN_ON
Restore the previous WARN_ON(cond) so that we don't complain about poor
old Cherryview.
Fixes: eb020ca3d43f ("drm/i915/display/dp: Make WARN* drm specific where drm_device ptr is available") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200223173959.3885742-1-chris@chris-wilson.co.uk
Pankaj Bharadiya [Thu, 20 Feb 2020 16:55:04 +0000 (22:25 +0530)]
drm/i915/display/dp: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
Pankaj Bharadiya [Thu, 20 Feb 2020 16:55:02 +0000 (22:25 +0530)]
drm/i915/display/display: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
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