Bjorn Helgaas [Wed, 5 Aug 2020 23:24:21 +0000 (18:24 -0500)]
Merge branch 'pci/host-probe-refactor'
- Use pci_host_bridge.windows list directly instead of splicing in a
temporary list for cadence, mvebu, host-common (Rob Herring)
- Use pci_host_probe() instead of open-coding all the pieces for altera,
brcmstb, iproc, mobiveil, rcar, rockchip, tegra, v3, versatile, xgene,
xilinx, xilinx-nwl (Rob Herring)
- Convert to devm_platform_ioremap_resource_byname() instead of open-coding
platform_get_resource_byname() and devm_ioremap_resource() for altera,
cadence, mediatek, rockchip, tegra, xgene (Dejin Zheng)
- Convert to devm_platform_ioremap_resource() instead of open-coding
platform_get_resource() and devm_ioremap_resource() for aardvark,
brcmstb, exynos, ftpci100, versatile (Dejin Zheng)
- Remove redundant error messages from devm_pci_remap_cfg_resource()
callers (Dejin Zheng)
- Drop useless PCI_ENABLE_PROC_DOMAINS from versatile driver (Rob Herring)
- Default host bridge parent device to the platform device (Rob Herring)
- Drop unnecessary zeroing of host bridge fields (Rob Herring)
- Use pci_is_root_bus() instead of tracking root bus number separately in
aardvark, designware (imx6, keystone, designware-host), mobiveil,
xilinx-nwl, xilinx, rockchip, rcar (Rob Herring)
- Set host bridge bus number in pci_scan_root_bus_bridge() instead of each
driver for aardvark, designware-host, host-common, mediatek, rcar, tegra,
v3-semi (Rob Herring)
- Use bridge resources instead of parsing DT 'ranges' again for cadence
(Rob Herring)
- Remove private bus number and range from cadence (Rob Herring)
- Use devm_pci_alloc_host_bridge() to simplify rcar (Rob Herring)
- Use struct pci_host_bridge.windows list directly rather than a temporary
(Rob Herring)
- Reduce OF "missing non-prefetchable window" from error to warning message
(Rob Herring)
- Convert rcar-gen2 from old Arm-specific pci_common_init_dev() to new
arch-independent interfaces (Rob Herring)
- Move DT resource setup into devm_pci_alloc_host_bridge() (Rob Herring)
- Set bridge map_irq and swizzle_irq to default functions; drivers that
don't support legacy IRQs (iproc) need to undo this (Rob Herring)
* pci/host-probe-refactor:
PCI: Set bridge map_irq and swizzle_irq to default functions
PCI: Move DT resource setup into devm_pci_alloc_host_bridge()
PCI: rcar-gen2: Convert to use modern host bridge probe functions
PCI: of: Reduce missing non-prefetchable memory region to a warning
PCI: rcar: Use struct pci_host_bridge.windows list directly
PCI: rcar: Use devm_pci_alloc_host_bridge()
PCI: cadence: Remove private bus number and range storage
PCI: cadence: Use bridge resources for outbound window setup
PCI: Move setting pci_host_bridge.busnr out of host drivers
PCI: rcar: Use pci_is_root_bus() to check if bus is root bus
PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus
PCI: xilinx: Use pci_is_root_bus() to check if bus is root bus
PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus
PCI: mobiveil: Use pci_is_root_bus() to check if bus is root bus
PCI: designware: Use pci_is_root_bus() to check if bus is root bus
PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus
PCI: Drop unnecessary zeroing of bridge fields
PCI: Set default bridge parent device
PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS
PCI: controller: Remove duplicate error message
PCI: controller: Convert to devm_platform_ioremap_resource()
PCI: controller: Convert to devm_platform_ioremap_resource_byname()
PCI: xilinx: Use pci_host_probe() to register host
PCI: xilinx-nwl: Use pci_host_probe() to register host
PCI: rockchip: Use pci_host_probe() to register host
PCI: rcar: Use pci_host_probe() to register host
PCI: iproc: Use pci_host_probe() to register host
PCI: altera: Use pci_host_probe() to register host
PCI: xgene: Use pci_host_probe() to register host
PCI: versatile: Use pci_host_probe() to register host
PCI: v3: Use pci_host_probe() to register host
PCI: tegra: Use pci_host_probe() to register host
PCI: mobiveil: Use pci_host_probe() to register host
PCI: brcmstb: Use pci_host_probe() to register host
PCI: host-common: Use struct pci_host_bridge.windows list directly
PCI: mvebu: Use struct pci_host_bridge.windows list directly
PCI: cadence: Use struct pci_host_bridge.windows list directly
Bjorn Helgaas [Wed, 5 Aug 2020 23:24:18 +0000 (18:24 -0500)]
Merge branch 'remotes/lorenzo/pci/dwc'
- Add qcom ipq806x support (Ansuel Smith)
- Support max-link-speed DT property for qcom (Sham Muthayyan)
- Use PCI core #defines instead of adding qcom-specific ones (Ansuel Smith)
- Convert to devm_platform_ioremap_resource_byname() instead of open-coding
platform_get_resource_byname() and devm_ioremap_resource() for dra7xx,
keystone, artpec6, designware-plat, histb, intel-gw, kirin, qcom,
uniphier (Dejin Zheng)
Bjorn Helgaas [Wed, 5 Aug 2020 23:24:18 +0000 (18:24 -0500)]
Merge branch 'remotes/lorenzo/pci/cadence'
- Convert cadence to use standard "dma-ranges" DT property instead of its
own "cdns,no-bar-match-nbits" (Kishon Vijay Abraham I)
- Fix pm_runtime_put_sync() issues in cadence error paths (Kishon Vijay
Abraham I)
- Add PTR_ALIGN_DOWN macro (Kishon Vijay Abraham I)
- Convert cadence r/w accessors to only 32-bit accesses (Kishon Vijay
Abraham I)
- Add cadence support to start Link and check Link status (Kishon Vijay
Abraham I)
- Allow custom PCI ops for cadence-based drivers (Kishon Vijay Abraham I)
- Remove "mem" from cadence reg binding since it's not memory and it
overlaps the PCIe config and memory region (Kishon Vijay Abraham I)
- Add cadence ->cpu_addr_fixup() for platforms that require absolute
addresses in the ATU, not just offsets (Kishon Vijay Abraham I)
- Update cadence Vendor IDs using local management registers, not
architected config space (Kishon Vijay Abraham I)
- Add cadence endpoint driver MSI-X support (Kishon Vijay Abraham I)
- Add bindings and driver for TI J721E SoC, supporting both host and
endpoint mode (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/cadence:
MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe
misc: pci_endpoint_test: Add J721E in pci_device_id table
PCI: j721e: Add TI J721E PCIe driver
dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC
dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
PCI: cadence: Add MSI-X support to Endpoint driver
PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register
PCI: cadence: Add new *ops* for CPU addr fixup
dt-bindings: PCI: cadence: Remove "mem" from reg binding
PCI: cadence: Allow pci_host_bridge to have custom pci_ops
PCI: cadence: Add support to start link and verify link status
PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses
linux/kernel.h: Add PTR_ALIGN_DOWN macro
PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property
Bjorn Helgaas [Wed, 5 Aug 2020 23:24:15 +0000 (18:24 -0500)]
Merge branch 'pci/error'
- Use pci_channel_state_t instead of enum pci_channel_state (Luc Van
Oostenryck)
- Simplify __aer_print_error() (Bjorn Helgaas)
- Log AER correctable errors as warning, not error (Matt Jolly)
- Rename pci_aer_clear_device_status() to pcie_clear_device_status() (Bjorn
Helgaas)
- Clear PCIe Device Status errors only if OS owns AER (Jonathan Cameron)
* pci/error:
PCI/ERR: Clear PCIe Device Status errors only if OS owns AER
PCI/ERR: Rename pci_aer_clear_device_status() to pcie_clear_device_status()
PCI/AER: Log correctable errors as warning, not error
PCI/AER: Simplify __aer_print_error()
PCI: Use 'pci_channel_state_t' instead of 'enum pci_channel_state'
Rob Herring [Wed, 22 Jul 2020 02:25:14 +0000 (20:25 -0600)]
PCI: Set bridge map_irq and swizzle_irq to default functions
The majority of DT based host drivers use the default .map_irq() and
.swizzle_irq() functions, so let's initialize the function pointers to
the default and drop setting them in the host drivers.
Drivers like iProc which don't support legacy interrupts need to set
.map_irq() back to NULL.
Link: https://lore.kernel.org/r/20200722022514.1283916-20-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
Rob Herring [Wed, 22 Jul 2020 02:25:13 +0000 (20:25 -0600)]
PCI: Move DT resource setup into devm_pci_alloc_host_bridge()
Now that pci_parse_request_of_pci_ranges() callers just setup
pci_host_bridge.windows and dma_ranges directly and don't need the bus
range returned, we can just initialize them when allocating the
pci_host_bridge struct.
With this, pci_parse_request_of_pci_ranges() becomes a static function.
Link: https://lore.kernel.org/r/20200722022514.1283916-19-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
Rob Herring [Wed, 22 Jul 2020 02:25:12 +0000 (20:25 -0600)]
PCI: rcar-gen2: Convert to use modern host bridge probe functions
The rcar-gen2 host driver still uses the old Arm PCI setup function
pci_common_init_dev(). Let's update it to use the modern
devm_pci_alloc_host_bridge(), pci_parse_request_of_pci_ranges() and
pci_host_probe() functions.
Link: https://lore.kernel.org/r/20200722022514.1283916-18-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-renesas-soc@vger.kernel.org
Add support for PCIe controller in J721E SoC. The controller uses the
Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller
will work in both host mode and device mode.
Some of the features of the controller are:
*) Supports both RC mode and EP mode
*) Supports MSI and MSI-X support
*) Supports upto GEN3 speed mode
*) Supports SR-IOV capability
*) Ability to route all transactions via SMMU (support will be added
in a later patch).
drivers/pci/hotplug/rpadlpar_core.c:355:5: warning: symbol 'dlpar_remove_pci_slot' was not declared. Should it be static?
drivers/pci/hotplug/rpadlpar_core.c:461:12: warning: symbol 'rpadlpar_io_init' was not declared. Should it be static?
drivers/pci/hotplug/rpadlpar_core.c:473:6: warning: symbol 'rpadlpar_io_exit' was not declared. Should it be static?
Those functions are not used outside of this file, so mark them static.
The error also makes graphics driver fail to probe the device.
It appears to be the same issue as commit 5e89cd303e3a ("PCI: Mark AMD
Navi14 GPU rev 0xc5 ATS as broken") addresses, and indeed the same ATS
quirk can workaround the issue.
See-also: 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken")
See-also: d28ca864c493 ("PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken")
See-also: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken")
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208725 Link: https://lore.kernel.org/r/20200728104554.28927-1-kai.heng.feng@canonical.com Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
388c8c16abaf ("PCI: add routines for debugging and handling lost
interrupts") added pci_lost_interrupt() that apparently never has had a
single user. Remove it.
Alan Douglas [Wed, 22 Jul 2020 11:03:12 +0000 (16:33 +0530)]
PCI: cadence: Add MSI-X support to Endpoint driver
Implement ->set_msix() and ->get_msix() callback functions in order
to configure MSIX capability in the PCIe endpoint controller.
Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host.
cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual
address) from "struct cdns_pcie_epf" that gets initialized in
->set_bar() call back function.
[kishon@ti.com: Re-implement MSIX support in accordance with the
re-designed core MSI-X interfaces] Link: https://lore.kernel.org/r/20200722110317.4744-11-kishon@ti.com Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
drivers/pci/controller/pci-hyperv.c:941:5: warning:
symbol 'hv_read_config_block' was not declared. Should it be static?
drivers/pci/controller/pci-hyperv.c:1021:5: warning:
symbol 'hv_write_config_block' was not declared. Should it be static?
drivers/pci/controller/pci-hyperv.c:1090:5: warning:
symbol 'hv_register_block_invalidate' was not declared. Should it be static?
Those functions are not used outside of this file, so mark them static.
Thierry Reding [Tue, 23 Jun 2020 14:55:28 +0000 (16:55 +0200)]
PCI: tegra: Remove PLL power supplies
The Tegra PCI controller driver doesn't need to control the PLL power
supplies directly, but rather uses the pads provided by the XUSB pad
controller, which in turn is responsible for supplying power to the
PLLs.
Thierry Reding [Tue, 23 Jun 2020 14:55:27 +0000 (16:55 +0200)]
dt-bindings: pci: tegra: Remove PLL power supplies
The XUSB pad controller, which provides access to various USB, PCI and
SATA pads (or PHYs), needs to bring up the PLLs associated with these
pads. In order to properly do so, it needs to control the power supplied
to these PLLs.
Remove the PLL power supplies from the PCIe controller because it does
not need direct access to them. Instead it will only use the configured
pads provided by the XUSB pad controller.
The HiSilicon non-ECAM PCIe has been broken since March 2016 commit 7e57fd1444bf ("PCI: designware: Move Root Complex setup code to
dw_pcie_setup_rc()"). The reason is this commit moved the iATU setup code
from dw_pcie_host_init() to dw_pcie_setup_rc(), but the hisi driver never
calls dw_pcie_setup_rc(). The result is the PCI memory space is never
configured and the driver can't work. It's also clear it has an iATU as
the config space accesses use it.
There's also no dts file using either "hisilicon,hip05-pcie" or
"hisilicon,hip06-pcie".
Link: https://lore.kernel.org/r/20200724224204.3249055-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register
Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe
controller") in order to update Vendor ID, directly wrote to
PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration
space is read-only register and writing to it will have no effect.
Use local management register to configure Vendor ID and Subsystem Vendor
ID.
Link: https://lore.kernel.org/r/20200722110317.4744-10-kishon@ti.com Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
Cadence driver uses "mem" memory resource to obtain the offset of
configuration space address region, memory space address region and
message space address region. The obtained offset is used to program
the Address Translation Unit (ATU). However certain platforms like TI's
J721E SoC require the absolute address to be programmed in the ATU and
not just the offset. Add new *ops* for CPU addr fixup for the platform
drivers to provide the correct address to be programmed in the ATU.
PCI: cadence: Allow pci_host_bridge to have custom pci_ops
Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
PCI: cadence: Add support to start link and verify link status
Add cdns_pcie_ops to start link and verify link status. The registers
to start link and to check link status is in Platform specific PCIe
wrapper. Add support for platform specific drivers to add callback
functions for the PCIe Cadence core to start link and verify link status.
PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses
Certain platforms like TI's J721E using Cadence PCIe IP can perform only
32-bit accesses for reading or writing to Cadence registers. Convert all
read and write accesses to 32-bit in Cadence PCIe driver in preparation
for adding PCIe support in TI's J721E SoC.
Also add spin lock to disable interrupts while modifying PCI_STATUS
register while raising legacy interrupt since PCI_STATUS is accessible
by both remote RC and EP and time between read and write should be
minimized.
Add a macro for aligning down a pointer. This is useful to get an
aligned register address when a device allows only word access and
doesn't allow half word or byte access.
commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core
library") while refactoring the Cadence PCIe driver to be used as
library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup()
and cdns_pcie_host_setup() but missed to remove the corresponding
pm_runtime_put_sync() in the error path. Fix it here.
Link: https://lore.kernel.org/r/20200722110317.4744-3-kishon@ti.com Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property
Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits"
property to configure the number of bits passed through from PCIe
address to internal address in Inbound Address Translation register.
This only used the NO MATCH BAR.
However standard PCI dt-binding already defines "dma-ranges" to
describe the address ranges accessible by PCIe controller. Add support
in Cadence PCIe host driver to parse dma-ranges and configure the
inbound regions for BAR0, BAR1 and NO MATCH BAR. Cadence IP specifies
maximum size for BAR0 as 256GB, maximum size for BAR1 as 2 GB.
This adds support to take the next biggest region in "dma-ranges" and
find the smallest BAR that each of the regions fit in and if there is
no BAR big enough to hold the region, split the region to see if it can
be fitted using multiple BARs.
"dma-ranges" of J721E will be
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
Since there is no BAR which can hold 2^48 size, NO_MATCH_BAR will be
used here.
Legacy device tree binding compatibility is maintained by retaining
support for "cdns,no-bar-match-nbits".
Wei Hu [Mon, 27 Jul 2020 07:17:31 +0000 (15:17 +0800)]
PCI: hv: Fix a timing issue which causes kdump to fail occasionally
Kdump could fail sometime on Hyper-V guest because the retry in
hv_pci_enter_d0() releases child device structures in hv_pci_bus_exit().
Although there is a second asynchronous device relations message sending
from the host, if this message arrives to the guest after
hv_send_resource_allocated() is called, the retry would fail.
Fix the problem by moving retry to hv_pci_probe() and start the retry
from hv_pci_query_relations() call. This will cause a device relations
message to arrive to the guest synchronously; the guest would then be
able to rebuild the child device structures before calling
hv_send_resource_allocated().
Link: https://lore.kernel.org/r/20200727071731.18516-1-weh@microsoft.com Fixes: c81992e7f4aa ("PCI: hv: Retry PCI bus D0 entry on invalid device state") Signed-off-by: Wei Hu <weh@microsoft.com>
[lorenzo.pieralisi@arm.com: fixed a comment and commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
PCI/ATS: Add pci_pri_supported() to check device or associated PF
For SR-IOV, the PF PRI is shared between the PF and any associated VFs, and
the PRI Capability is allowed for PFs but not for VFs. Searching for the
PRI Capability on a VF always fails, even if its associated PF supports
PRI.
Add pci_pri_supported() to check whether device or its associated PF
supports PRI.
Colin Ian King [Thu, 11 Jun 2020 12:31:34 +0000 (13:31 +0100)]
xen: Remove redundant initialization of irq
The variable irq is being initialized with a value that is never read
and it is being updated later with a new value. The initialization is
redundant and can be removed.
Rob Herring [Wed, 22 Jul 2020 02:25:11 +0000 (20:25 -0600)]
PCI: of: Reduce missing non-prefetchable memory region to a warning
The pci-rcar-gen2 controller requires only a prefetchable memory region,
and the error prevents using pci_parse_request_of_pci_ranges() for it.
Let's reduce this to just a warning message so this function can be used
for pci-rcar-gen2.
Link: https://lore.kernel.org/r/20200722022514.1283916-17-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Rob Herring [Wed, 22 Jul 2020 02:25:10 +0000 (20:25 -0600)]
PCI: rcar: Use struct pci_host_bridge.windows list directly
There's no need to create a temporary resource list and then splice it to
struct pci_host_bridge.windows list. Just use pci_host_bridge.windows
directly. The necessary clean-up is already handled by the PCI core.
Link: https://lore.kernel.org/r/20200722022514.1283916-16-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org
Rob Herring [Wed, 22 Jul 2020 02:25:06 +0000 (20:25 -0600)]
PCI: Move setting pci_host_bridge.busnr out of host drivers
Most host drivers only parse the DT bus range to set the root bus number
in pci_host_bridge.busnr. The ones that don't set busnr are buggy in
that they ignore what's in DT. Let's set busnr in pci_scan_root_bus_bridge()
where we already check for the bus resource and remove setting it in
host drivers.
Link: https://lore.kernel.org/r/20200722022514.1283916-12-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Will Deacon <will@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Ryder Lee <ryder.lee@mediatek.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: linux-tegra@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org
Rob Herring [Wed, 22 Jul 2020 02:25:05 +0000 (20:25 -0600)]
PCI: rcar: Use pci_is_root_bus() to check if bus is root bus
Use pci_is_root_bus() rather than tracking the root bus number to
determine if the bus is the root bus or not. This removes storing
duplicated data as well as the need for the host bridge driver to have
to care about the bus numbers in most cases.
Link: https://lore.kernel.org/r/20200722022514.1283916-11-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-renesas-soc@vger.kernel.org
Rob Herring [Wed, 22 Jul 2020 02:25:04 +0000 (20:25 -0600)]
PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus
Use pci_is_root_bus() rather than tracking the root bus number to
determine if the bus is the root bus or not. This removes storing
duplicated data as well as the need for the host bridge driver to have
to care about the bus numbers in most cases.
Also, bridge->busnr is never set so effectively the root bus must be 0.
This will be fixed by a subsequent commit.
Link: https://lore.kernel.org/r/20200722022514.1283916-10-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Shawn Lin <shawn.lin@rock-chips.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-rockchip@lists.infradead.org
Rob Herring [Wed, 22 Jul 2020 02:25:03 +0000 (20:25 -0600)]
PCI: xilinx: Use pci_is_root_bus() to check if bus is root bus
Use pci_is_root_bus() rather than tracking the root bus number to
determine if the bus is the root bus or not. This removes storing
duplicated data as well as the need for the host bridge driver to have
to care about the bus numbers in most cases.
There was also a bug that the root_busno is never set which means the
root bus number is always 0 even if the DT said something else.
Link: https://lore.kernel.org/r/20200722022514.1283916-9-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org
Rob Herring [Wed, 22 Jul 2020 02:25:02 +0000 (20:25 -0600)]
PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus
Use pci_is_root_bus() rather than tracking the root bus number to
determine if the bus is the root bus or not. This removes storing
duplicated data as well as the need for the host bridge driver to have
to care about the bus numbers in most cases.
There was also a bug that the pci_host_bridge.busnr is set from
root_busno, but root_busno is never set which means the root bus number
is always 0 even if the DT said something else.
Link: https://lore.kernel.org/r/20200722022514.1283916-8-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com>
Rob Herring [Wed, 22 Jul 2020 02:25:01 +0000 (20:25 -0600)]
PCI: mobiveil: Use pci_is_root_bus() to check if bus is root bus
Use pci_is_root_bus() rather than tracking the root bus number to
determine if the bus is the root bus or not. This removes storing
duplicated data as well as the need for the host bridge driver to have
to care about the bus numbers in most cases.
Link: https://lore.kernel.org/r/20200722022514.1283916-7-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
Rob Herring [Wed, 22 Jul 2020 02:25:00 +0000 (20:25 -0600)]
PCI: designware: Use pci_is_root_bus() to check if bus is root bus
Use pci_is_root_bus() rather than tracking the root bus number to
determine if the bus is the root bus or not. This removes storing
duplicated data as well as the need for the host bridge driver to have
to care about the bus numbers in most cases.
Link: https://lore.kernel.org/r/20200722022514.1283916-6-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Rob Herring [Wed, 22 Jul 2020 02:24:59 +0000 (20:24 -0600)]
PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus
Use pci_is_root_bus() rather than tracking the root bus number to
determine if the bus is the root bus or not. This removes storing
duplicated data as well as the need for the host bridge driver to have
to care about the bus numbers in most cases.
Link: https://lore.kernel.org/r/20200722022514.1283916-5-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
Rob Herring [Wed, 22 Jul 2020 02:24:57 +0000 (20:24 -0600)]
PCI: Set default bridge parent device
The host bridge's parent device is always the platform device. As we
already have a pointer to it in the devres functions, let's initialize
the parent device. Drivers can still override the parent if desired.
Link: https://lore.kernel.org/r/20200722022514.1283916-3-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
Rob Herring [Wed, 22 Jul 2020 02:24:56 +0000 (20:24 -0600)]
PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS
PCI_ENABLE_PROC_DOMAINS is only used on powerpc and doesn't do anything
for the Versatile host driver, so let's drop it. I'm not sure how or why
I had this to begin with. PCI_ENABLE_PROC_DOMAINS was never used on ARM.
Link: https://lore.kernel.org/r/20200722022514.1283916-2-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
Dinghao Liu [Thu, 9 Jul 2020 06:43:56 +0000 (14:43 +0800)]
PCI: rcar: Fix runtime PM imbalance on error
pm_runtime_get_sync() increments the runtime PM usage counter even
when the call returns an error code. Thus a corresponding decrement is
needed on the error handling path to keep the counter balanced.
Link: https://lore.kernel.org/r/20200709064356.8800-1-dinghao.liu@zju.edu.cn Fixes: 0df6150e7ceb ("PCI: rcar: Use runtime PM to control controller clock") Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Jonathan Cameron [Mon, 22 Jun 2020 11:35:23 +0000 (19:35 +0800)]
PCI/ERR: Clear PCIe Device Status errors only if OS owns AER
pcie_clear_device_status() resets the error bits in the PCIe Device Status
Register (PCI_EXP_DEVSTA).
Previously we did this unconditionally, but on ACPI systems, the _OSC AER
bit negotiates control of the AER capability. Per sec 4.5.1 of the System
Firmware Intermediary _OSC and DPC Updates ECN [1], this bit also covers
other error enable/status bits including the following:
These bits are all in the PCIe Device Control register (the ECN omitted
"Reporting", but I think that's a typo), so by implication the _OSC AER bit
also applies to the error status bits in the PCIe Device Status register:
Clear the PCIe Device Status error bits only when the OS controls the AER
capability and related error enable/status bits. If platform firmware
controls the AER capability, firmware is responsible for clearing these
bits.
PCI/ERR: Rename pci_aer_clear_device_status() to pcie_clear_device_status()
pci_aer_clear_device_status() clears the error bits in the PCIe Device
Status Register (PCI_EXP_DEVSTA). Every PCIe device has this register,
regardless of whether it supports AER.
Rename pci_aer_clear_device_status() to pcie_clear_device_status() to make
clear that it is PCIe-specific but not AER-specific. Move it to
drivers/pci/pci.c, again since it's not AER-specific. No functional change
intended.
PCI: aardvark: Don't touch PCIe registers if no card connected
When there is no PCIe card connected and advk_pcie_rd_conf() or
advk_pcie_wr_conf() is called for PCI bus which doesn't belong to emulated
root bridge, the aardvark driver throws the following error message:
advk-pcie d0070000.pcie: config read/write timed out
Obviously accessing PCIe registers of disconnected card is not possible.
Extend check in advk_pcie_valid_device() function for validating
availability of PCIe bus. If PCIe link is down, then the device is marked
as Not Found and the driver does not try to access these registers.
This is just an optimization to prevent accessing PCIe registers when card
is disconnected. Trying to access PCIe registers of disconnected card does
not cause any crash, kernel just needs to wait for a timeout. So if card
disappear immediately after checking for PCIe link (before accessing PCIe
registers), it does not cause any problems.
Tiezhu Yang [Sat, 18 Jul 2020 09:39:36 +0000 (17:39 +0800)]
PCI: loongson: Use DECLARE_PCI_FIXUP_EARLY for bridge_class_quirk()
According to the datasheet of Loongson LS7A bridge chip, the old version
of Loongson LS7A PCIE port has a wrong value about PCI class which is
0x060000, the correct value should be 0x060400, this bug can be fixed by
"dev->class = PCI_CLASS_BRIDGE_PCI << 8;" at the software level and it
was fixed in hardware in the latest LS7A versions.
In order to maintain downward compatibility, use DECLARE_PCI_FIXUP_EARLY
instead of DECLARE_PCI_FIXUP_HEADER for bridge_class_quirk() to fix it as
early as possible.
Otherwise, in the function pci_setup_device(), the related code about
"dev->class" such as "class = dev->class >> 8;" and "dev->transparent
= ((dev->class & 0xff) == 1);" maybe get wrong value without EARLY fixup.
After that, the ethernet NIC is not functional anymore even after
reloading the r8169 module. After a reboot, this is reproducible by
copying a large file over the NIC to the MMC.
For some reason this is not reproducible when files are copied to a tmpfs.
* Little background on the fixup, by Manikanta Maddireddy:
"In the internal testing with dGPU on Tegra124, CmplTO is reported by
dGPU. This happened because FIFO queue in AFI(AXI to PCIe) module
get full by upstream posted writes. Back to back upstream writes
interleaved with infrequent reads, triggers RAW violation and CmpltTO.
This is fixed by reducing the posted write credits and by changing
updateFC timer frequency. These settings are fixed after stress test.
In the current case, RTL NIC is also reporting CmplTO. These settings
seems to be aggravating the issue instead of fixing it."
Link: https://lore.kernel.org/r/20200718100710.15398-1-kwizart@gmail.com Fixes: 191cd6fb5d2c ("PCI: tegra: Add SW fixup for RAW violations") Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Cc: stable@vger.kernel.org
PCI: dwc: Convert to devm_platform_ioremap_resource_byname()
Use devm_platform_ioremap_resource_byname() to simplify the code
since it contains platform_get_resource_byname() and
devm_ioremap_resource() respectively.
Link: https://lore.kernel.org/r/20200708164013.5076-1-zhengdejin5@gmail.com Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Reviewed-by: Rob Herring <robh@kernel.org>
Shmuel Hazan [Tue, 23 Jun 2020 06:03:35 +0000 (09:03 +0300)]
PCI: mvebu: Setup BAR0 in order to fix MSI
According to the Armada XP datasheet, section 10.2.6: "in order for
the device to do a write to the MSI doorbell address, it needs to write
to a register in the internal registers space".
As a result of the requirement above, without this patch, MSI won't
function and therefore some devices won't operate properly without
pci=nomsi.
This requirement was not present at the time of writing this driver
since the vendor u-boot always initializes all PCIe controllers
(incl. BAR0 initialization) and for some time, the vendor u-boot was
the only available bootloader for this driver's SoCs (e.g. A38x,A37x,
etc).
Tested on an Armada 385 board on mainline u-boot (2020.4), without
u-boot PCI initialization and the following PCIe devices:
- Wilocity Wil6200 rev 2 (wil6210)
- Qualcomm Atheros QCA6174 (ath10k_pci)
Both failed to get a response from the device after loading the
firmware and seem to operate properly with this patch.
Qiushi Wu [Thu, 28 May 2020 02:13:22 +0000 (21:13 -0500)]
PCI: Fix pci_create_slot() reference count leak
kobject_init_and_add() takes a reference even when it fails. If it returns
an error, kobject_put() must be called to clean up the memory associated
with the object.
When kobject_init_and_add() fails, call kobject_put() instead of kfree().
b8eb718348b8 ("net-sysfs: Fix reference count leak in
rx|netdev_queue_add_kobject") fixed a similar problem.
Rajat Jain [Tue, 7 Jul 2020 22:46:03 +0000 (15:46 -0700)]
PCI: Treat "external-facing" devices themselves as internal
"External-facing" devices are internal devices that expose PCIe hierarchies
such as Thunderbolt outside the platform [1]. Previously these internal
devices were marked as "untrusted" the same as devices downstream from
them.
Use the ACPI or DT information to identify external-facing devices, but
only mark the devices *downstream* from them as "untrusted" [2]. The
external-facing device itself is no longer marked as untrusted.
Rajat Jain [Tue, 7 Jul 2020 22:46:02 +0000 (15:46 -0700)]
PCI: Cache ACS capability offset in device
Currently the ACS capability is being looked up at a number of places. Read
and store it once at enumeration so that it can be used by all later. No
functional change intended.
Dejin Zheng [Tue, 2 Jun 2020 17:16:01 +0000 (01:16 +0800)]
PCI: controller: Convert to devm_platform_ioremap_resource_byname()
Use devm_platform_ioremap_resource_byname() to simplify the code,
since it calls respectively platform_get_resource_byname() and
devm_ioremap_resource().
Link: https://lore.kernel.org/r/20200602171601.17630-1-zhengdejin5@gmail.com Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Rob Herring [Fri, 22 May 2020 23:48:32 +0000 (17:48 -0600)]
PCI: xilinx: Use pci_host_probe() to register host
The xilinx host driver does the same host registration and bus scanning
calls as pci_host_probe, so let's use it instead.
The only difference is pci_assign_unassigned_bus_resources() was called
instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This
should be the same.
Rob Herring [Fri, 22 May 2020 23:48:31 +0000 (17:48 -0600)]
PCI: xilinx-nwl: Use pci_host_probe() to register host
The xilinx-nwl host driver does the same host registration and bus scanning
calls as pci_host_probe, so let's use it instead.
The only difference is pci_assign_unassigned_bus_resources() was called
instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This
should be the same.
Rob Herring [Fri, 22 May 2020 23:48:28 +0000 (17:48 -0600)]
PCI: iproc: Use pci_host_probe() to register host
The iproc host driver does the same host registration and bus scanning
calls as pci_host_probe, so let's use it instead.
The only difference is pci_assign_unassigned_bus_resources() was called
instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This
should be the same.
Link: https://lore.kernel.org/r/20200522234832.954484-12-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com
Rob Herring [Fri, 22 May 2020 23:48:27 +0000 (17:48 -0600)]
PCI: altera: Use pci_host_probe() to register host
The altera host driver does the same host registration and bus scanning
calls as pci_host_probe, so let's use it instead.
The only difference is pci_assign_unassigned_bus_resources() was called
instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This
should be the same.
Link: https://lore.kernel.org/r/20200522234832.954484-11-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: rfi@lists.rocketboards.org
Rob Herring [Fri, 22 May 2020 23:48:20 +0000 (17:48 -0600)]
PCI: host-common: Use struct pci_host_bridge.windows list directly
There's no need to create a temporary resource list and then splice it to
struct pci_host_bridge.windows list. Just use pci_host_bridge.windows
directly. The necessary clean-up is already handled by the PCI core.
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