Even for the mock i915 device, we need to initialise the
drm.mode_config, as we may ultimately query whether there are any KMS
users deep in the bowels of some paths (e.g. eviction). As we initialise
drm.mode_config we must cleanup after ourselves!
Chris Wilson [Fri, 8 Dec 2017 21:46:16 +0000 (21:46 +0000)]
agp/intel: Flush all chipset writes after updating the GGTT
Before accessing the GGTT we must flush the PTE writes and make them
visible to the chipset, or else the indirect access may end up in the
wrong page. In commit 3497971a71d8 ("agp/intel: Flush chipset writes
after updating a single PTE"), we noticed corruption of the uploads for
pwrite and for capturing GPU error states, but it was presumed that the
explicit calls to intel_gtt_chipset_flush() were sufficient for the
execbuffer path. However, we have not been flushing the chipset between
the PTE writes and access via the GTT itself.
For simplicity, do the flush after any PTE update rather than try and
batch the flushes on a just-in-time basis.
References: 3497971a71d8 ("agp/intel: Flush chipset writes after updating a single PTE") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: drm-intel-fixes@lists.freedesktop.org Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171208214616.30147-1-chris@chris-wilson.co.uk
Chris Wilson [Fri, 8 Dec 2017 01:23:03 +0000 (01:23 +0000)]
drm/i915: Add is-wedged flag to intel_engine_dump()
Comparing the state tested by intel_engine_is_idle() and printed by
intel_engine_dump(), the only bit not shown is whether or not the device
is wedged. Add that little bit of information to the pretty printer so
that if the engine fails to idle we can see why.
Chris Wilson [Fri, 8 Dec 2017 01:23:02 +0000 (01:23 +0000)]
drm/i915: Include the global reset count for intel_engine_dump()
Since a global reset affects the engine, include that along side the
per-engine reset counter when pretty printing the engine state in
intel_engine_dump().
Chris Wilson [Fri, 8 Dec 2017 01:23:01 +0000 (01:23 +0000)]
drm/i915: Include engine state on detecting a missed breadcrumb/seqno
Now that we have a common engine state pretty printer, we can use that
instead of the adhoc information printed when we miss a breadcrumb.
v2: Rearrange intel_engine_disarm_breadcrumbs() to avoid calling
intel_engine_dump() under the rb spinlock (Mika) and to pretty-print the
error state early so that we include the full list of waiters.
v3: Pass missed breadcrumb msg to pretty-printer as the header
v4: Preserve DRM_DEBUG_DRIVER filtering.
Chris Wilson [Fri, 8 Dec 2017 01:23:00 +0000 (01:23 +0000)]
drm/i915: Make engine state pretty-printer header configurable
Pass in a format string (and args) to specify the header to be emitted
along with the engine state when pretty-printing. This allows the header
to be emitted inside the drm_printer stream, so sharing the same prefix
and output characteristics (e.g. debug level and filtering).
Chris Wilson [Fri, 8 Dec 2017 01:22:59 +0000 (01:22 +0000)]
drm/i915: Use snprintf to avoid line-break when pretty-printing engines
When printing the execlist ports, we first print the ELSP header then
follow it with the pretty-printed request. Since switching to
drm_printer and show the output via printk, it automatically appends a
newline to each call (unlike the old seq_printf output). To avoid the
unwanted line break, construct the ELSP request header in a temporary
buffer.
Chris Wilson [Thu, 7 Dec 2017 22:00:25 +0000 (22:00 +0000)]
drm/i915: Drop fb reference on load_detect_pipe failure path
When intel_modeset_setup_plane_state() fails drop the local framebuffer
reference before jumping to the error, otherwise we leak the framebuffer.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Fixes: edde361711ef ("drm/i915: Use atomic state to obtain load detection crtc, v3.") Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171207220025.22698-1-chris@chris-wilson.co.uk
Daniel Vetter [Thu, 7 Dec 2017 14:32:02 +0000 (15:32 +0100)]
intel/atomic: Stop updating legacy fb parameters
Even fbc isn't using this stuff anymore, so time to remove it.
Cleaning up one small piece of the atomic conversion cruft at the time
...
Quick explanation on why the plane->fb assignment is ok to delete: The
core code takes care of the refcounting and legacy ->fb pointer
updating, but drivers are allowed to update it ahead of time. Most
legacy modeset drivers did that as part of their set_config callback
(since that's how the legacy/crtc helpers worked). In i915 we only
need that to make the fbc code happy.
v2: don't nuke the assignement of intel_crtc->config, I accidentally
set CI ablaze :-) Spotted by Maarten. And better explain why nuking
the ->fb assignement shouldn't set off alarm bells.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171207143202.6021-1-daniel.vetter@ffwll.ch
Tvrtko Ursulin [Tue, 5 Dec 2017 13:28:54 +0000 (13:28 +0000)]
drm/i915: Restore GT performance in headless mode with DMC loaded
It seems that the DMC likes to transition between the DC states a lot when
there are no connected displays (no active power domains) during command
submission.
This activity on DC states has a negative impact on the performance of the
chip with huge latencies observed in the interrupt handlers and elsewhere.
Simple tests like igt/gem_latency -n 0 are slowed down by a factor of
eight.
Work around it by introducing a new power domain named,
POWER_DOMAIN_GT_IRQ, associtated with the "DC off" power well, which is
held for the duration of command submission activity.
CNL has the same problem which will be addressed as a follow-up. Doing
that requires a fix for a DC6 context corruption problem in the CNL DMC
firmware which is yet to be released.
v2:
* Add commit text as comment in i915_gem_mark_busy. (Chris Wilson)
* Protect macro body with braces. (Jani Nikula)
v3:
* Add dedicated power domain for clarity. (Chris, Imre)
* Commit message and comment text updates.
* Apply to all big-core GEN9 parts apart for Skylake which is pending DMC
firmware release.
v4:
* Power domain should be inner to device runtime pm. (Chris)
* Simplify NEEDS_CSR_GT_PERF_WA macro. (Chris)
* Handle async DMC loading by moving the GT_IRQ power domain logic into
intel_runtime_pm. (Daniel, Chris)
* Include small core GEN9 as well. (Imre)
v5
* Special handling for async DMC load is not needed since on failure the
power domain reference is kept permanently taken. (Imre)
v6:
* Drop the NEEDS_CSR_GT_PERF_WA macro since all firmwares have now been
deployed. (Imre, Chris)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100572
Testcase: igt/gem_exec_nop/headless Cc: Imre Deak <imre.deak@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> (v2) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v5) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[Imre: Add note about applying the WA on CNL as a follow-up] Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171205132854.26380-1-tvrtko.ursulin@linux.intel.com
Chris Wilson [Thu, 7 Dec 2017 22:24:34 +0000 (22:24 +0000)]
drm/i915/execlists: Cache ELSP register offset
Currently on every submission, we recalculate the ELSP register offset
for the engine, after chasing the pointers to find the iomem base. Since
this is fixed for the lifetime of the driver, record the offset in the
execlists struct.
In practice the difference is negligible, it just happens to remove 27
bytes of eyesore pointer dancing from next to the hottest instruction
(which is itself due to stalling for a cache miss) in perf profiles of
the execlists_submission_tasklet().
Chris Wilson [Thu, 7 Dec 2017 21:14:07 +0000 (21:14 +0000)]
drm/i915: Refactor common list iteration over GGTT vma
In quite a few places, we have a list iteration over the vma on an
object that only want to inspect GGTT vma. By construction, these are
placed at the start of the list, so we have copied that knowledge into
many callsites. Pull that knowledge back to i915_vma.h and provide a
for_each_ggtt_vma() to tidy up the code.
v2: Add a backreference from vma_create() to remind ourselves why we put
ggtt vma at the head of the obj->vma_list (and ppgtt vma at the tail).
v3: Fixup s/vma/V/
Dave Airlie [Thu, 7 Dec 2017 22:39:14 +0000 (08:39 +1000)]
Merge tag 'drm-intel-next-2017-12-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
[airlied: fix conflict in intel_dsi.c]
drm-intel-next-2017-12-01:
- Init clock gate fix (Ville)
- Execlists event handling corrections (Chris, Michel)
- Improvements on GPU Cache invalidation and context switch (Chris)
- More perf OA changes (Lionel)
- More selftests improvements and fixes (Chris, Matthew)
- Clean-up on modules parameters (Chris)
- Clean-up around old ringbuffer submission and hw semaphore on old platforms (Chris)
- More Cannonlake stabilization effort (David, James)
- Display planes clean-up and improvements (Ville)
- New PMU interface for perf queries... (Tvrtko)
- ... and other subsequent PMU changes and fixes (Tvrtko, Chris)
- Remove success dmesg noise from rotation (Chris)
- New DMC for Kabylake (Anusha)
- Fixes around atomic commits (Daniel)
- GuC updates and fixes (Sagar, Michal, Chris)
- Couple gmbus/i2c fixes (Ville)
- Use exponential backoff for all our wait_for() (Chris)
- Fixes for i915/fbdev (Chris)
- Backlight fixes (Arnd)
- Updates on shrinker (Chris)
- Make Hotplug enable more robuts (Chris)
- Disable huge pages (TPH) on lack of a needed workaround (Joonas)
- New GuC images for SKL, KBL, BXT (Sagar)
- Add HW Workaround for Geminilake performance (Valtteri)
- Fixes for PPS timings (Imre)
- More IPS fixes (Maarten)
- Many fixes for Display Port on gen2-gen4 (Ville)
- Retry GPU reset making the recover from hang more robust (Chris)
* tag 'drm-intel-next-2017-12-01' of git://anongit.freedesktop.org/drm/drm-intel: (101 commits)
drm/i915: Update DRIVER_DATE to 20171201
drm/i915/cnl: Mask previous DDI - PLL mapping
drm/i915: Remove unsafe i915.enable_rc6
drm/i915: Sleep and retry a GPU reset if at first we don't succeed
drm/i915: Interlaced DP output doesn't work on VLV/CHV
drm/i915: Pass crtc state to intel_pipe_{enable,disable}()
drm/i915: Wait for pipe to start on i830 as well
drm/i915: Fix vblank timestamp/frame counter jumps on gen2
drm/i915: Fix deadlock in i830_disable_pipe()
drm/i915: Fix has_audio readout for DDI A
drm/i915: Don't add the "force audio" property to DP connectors that don't support audio
drm/i915: Disable DP audio for g4x
drm/i915/selftests: Wake the device before executing requests on the GPU
drm/i915: Set fake_vma.size as well as fake_vma.node.size for capture
drm/i915: Tidy up signed/unsigned comparison
drm/i915: Enable IPS with only sprite plane visible too, v4.
drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3.
drm/i915: Avoid PPS HW/SW state mismatch due to rounding
drm/i915: Skip switch-to-kernel-context on suspend when wedged
drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
...
Dave Airlie [Thu, 7 Dec 2017 22:15:54 +0000 (08:15 +1000)]
Merge tag 'drm-misc-next-2017-12-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
UAPI Changes:
- Add "panel orientation" property to DRM to indicate orientation of the
panel vs the device's casing (Hans de Goede)
Core Changes:
- misc doc and bug fixes
Driver Changes:
- sun4i: Many improvements to the DE driver like multi-plane support and
YUV formats (Jernej Skrabec)
* tag 'drm-misc-next-2017-12-07' of git://anongit.freedesktop.org/drm/drm-misc: (50 commits)
drm/sun4i: Fix uninitialized variables in vi layer
drm/fb-helper: Fix potential NULL pointer dereference
gpu: drm: stm: Adopt SPDX identifiers
gpu: drm: sti: Adopt SPDX identifiers
drm/fsl-dcu: Use drm_mode_config_helper_suspend/resume()
drm/sun4i: Wire in DE2 YUV support
drm/sun4i: Expand DE2 scaler lib with YUV support
drm/sun4i: Add DE2 definitions for YUV formats
drm/sun4i: Add DE2 CSC library
drm/sun4i: Add CCSC property to DE2 configuration
drm/sun4i: Add support for HW scaling to DE2
drm/sun4i: Add scaler configuration to DE2 mixers
drm/sun4i: Add support for DE2 VI planes
drm/sun4i: Reorganize UI layer code in DE2
drm/sun4i: Add support for all HW supported DE2 RGB formats
drm/sun4i: Add multi plane support to DE2 driver
drm/sun4i: Move interlace related code in DE2
drm/sun4i: Move channel size related code in DE2
drm/sun4i: Move line width setting in DE2
drm/sun4i: Use values calculated by atomic check
...
Chris Wilson [Wed, 6 Dec 2017 12:49:14 +0000 (12:49 +0000)]
drm/i915: Track GGTT writes on the vma
As writes through the GTT and GGTT PTE updates do not share the same
path, they are not strictly ordered and so we must explicitly flush the
indirect writes prior to modifying the PTE. We do track outstanding GGTT
writes on the object itself, but since the object may have multiple GGTT
vma, that is overly coarse as we can track and flush individual vma as
required.
Whilst here, update the GGTT flushing behaviour for Cannonlake.
v2: Hard-code ring offset to allow use during unload (after RCS may have
been freed, or never existed!)
Chris Wilson [Wed, 6 Dec 2017 12:49:13 +0000 (12:49 +0000)]
drm/i915: Remove vma from object on destroy, not close
Originally we translated from the object to the vma by walking
obj->vma_list to find the matching vm (for user lookups). Now we process
user lookups using the rbtree, and we only use obj->vma_list itself for
maintaining state (e.g. ensuring that all vma are flushed or rebound).
As such maintenance needs to go on beyond the user's awareness of the
vma, defer removal of the vma from the obj->vma_list from i915_vma_close()
to i915_vma_destroy()
Fixes: 5888fc9eac3c ("drm/i915: Flush pending GTT writes before unbinding")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104155 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171206124914.19960-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Dave Airlie [Wed, 6 Dec 2017 20:28:22 +0000 (06:28 +1000)]
Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next
First feature request for 4.16. Highlights:
- RV and Vega header cleanups
- TTM operation context support
- 48 bit GPUVM fixes for Vega/RV
- More smatch fixes
- ECC support for vega10
- Resizeable BAR support
- Multi-display sync support in DC
- SR-IOV fixes
- Various scheduler improvements
- GPU reset fixes and vram lost tracking
- Clean up DC/powerplay interfaces
- DCN display fixes
- Various DC fixes
* 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux: (291 commits)
drm/radeon: Use drm_fb_helper_lastclose() and _poll_changed()
drm/amdgpu: Use drm_fb_helper_lastclose() and _poll_changed()
drm/amd/display: Use drm_fb_helper_poll_changed()
drm/ttm: swap consecutive allocated pooled pages v4
drm/amdgpu: fix amdgpu_sync_resv v2
drm/ttm: swap consecutive allocated cached pages v3
drm/amd/amdgpu: set gtt size according to system memory size only
drm/amdgpu: Get rid of dep_sync as a seperate object.
drm/amdgpu: allow specifying vm_block_size for multi level PDs v2
drm/amdgpu: move validation of the VM size into the VM code
drm/amdgpu: allow non pot VM size values
drm/amdgpu: choose number of VM levels based on VM size
drm/amdgpu: unify VM size handling of Vega10 with older generation
drm/amdgpu: fix amdgpu_vm_num_entries
drm/amdgpu: fix VM PD addr shift
drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)
drm/amd/display: Don't call dm_log_to_buffer directly in dc_conn_log
drm/amd/display: Add dm_logger_append_va API
drm/ttm: Use a static string instead of an array of char *
drm/amd/display: remove usage of legacy_cursor_update
...
Noralf Trønnes [Tue, 5 Dec 2017 18:25:02 +0000 (19:25 +0100)]
drm/radeon: Use drm_fb_helper_lastclose() and _poll_changed()
This driver can use drm_fb_helper_lastclose() in its .lastclose function.
It can also use drm_fb_helper_output_poll_changed() as its
.output_poll_changed callback.
Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Noralf Trønnes [Tue, 5 Dec 2017 18:24:55 +0000 (19:24 +0100)]
drm/amdgpu: Use drm_fb_helper_lastclose() and _poll_changed()
This driver can use drm_fb_helper_lastclose() in its .lastclose function.
It can also use drm_fb_helper_output_poll_changed() as its
.output_poll_changed callback.
Remove the unused driver implementations.
Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 4 Dec 2017 10:26:14 +0000 (11:26 +0100)]
drm/ttm: swap consecutive allocated pooled pages v4
When we detect consecutive allocation of pages swap them to avoid
accidentally freeing them as huge page.
v2: use swap
v3: check if it's really the first allocated page
v4: don't touch the loop variable
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger He <Hongbo.He@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 24 Nov 2017 10:41:52 +0000 (11:41 +0100)]
drm/amdgpu: fix amdgpu_sync_resv v2
Fixes a bug introduced by AMDGPU_GEM_CREATE_EXPLICIT_SYNC. We still need
to wait for pipelined moves in the shared fences list.
v2: fix typo
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
When we detect consecutive allocation of pages swap them to avoid
accidentally freeing them as huge page.
v2: use swap
v3: check if it's really the first allocated page
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger He <Hongbo.He@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger He [Wed, 29 Nov 2017 09:12:03 +0000 (17:12 +0800)]
drm/amd/amdgpu: set gtt size according to system memory size only
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Get rid of dep_sync as a seperate object.
Instead mark fence as explicit in it's amdgpu_sync_entry.
v2:
Fix use after free bug and add new parameter description. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 27 Nov 2017 15:22:05 +0000 (16:22 +0100)]
drm/amdgpu: allow specifying vm_block_size for multi level PDs v2
This patch allows specifying the vm_block_size even when multi level
page directories are active.
v2: fix signed/unsigned compare warning
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 23 Nov 2017 11:57:18 +0000 (12:57 +0100)]
drm/amdgpu: move validation of the VM size into the VM code
This moves validation of the VM size parameter into amdgpu_vm_adjust_size().
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 23 Nov 2017 10:23:18 +0000 (11:23 +0100)]
drm/amdgpu: allow non pot VM size values
The VM size actually doesn't need to be a power of two.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 23 Nov 2017 10:16:05 +0000 (11:16 +0100)]
drm/amdgpu: choose number of VM levels based on VM size
This allows us limiting the VM size for testing even of Vega10.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 22 Nov 2017 16:00:35 +0000 (17:00 +0100)]
drm/amdgpu: unify VM size handling of Vega10 with older generation
One function to rule them all.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 20 Nov 2017 13:29:01 +0000 (14:29 +0100)]
drm/amdgpu: fix amdgpu_vm_num_entries
The block size only affects the leave nodes, everything else is fixed.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 27 Nov 2017 13:01:51 +0000 (14:01 +0100)]
drm/amdgpu: fix VM PD addr shift
The block size only affects the leave nodes, everything else is fixed.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 6 Nov 2017 07:34:55 +0000 (15:34 +0800)]
drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)
1. program vce 4.0 fw with 48 bit address
2. correct vce 4.0 fw stack and date offset
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Tue, 28 Nov 2017 11:06:13 +0000 (12:06 +0100)]
drm/amd/display: Don't call dm_log_to_buffer directly in dc_conn_log
dm_log_to_buffer logs unconditionally, so calling it directly resulted
in the main message being logged even when the event type isn't enabled
in the event mask.
To fix this, use the new dm_logger_append_va API.
Fixes spurious messages like
[drm] {1920x1200, 2080x1235@154000Khz}
in dmesg when a mode is set.
v2:
* Use new dm_logger_append_va API, fixes incorrect va_list usage in v1
* Just use and decrease entry.buf_offset to get rid of the trailing
newline
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Tue, 28 Nov 2017 11:06:13 +0000 (12:06 +0100)]
drm/amd/display: Add dm_logger_append_va API
Same as dm_logger_append, except it takes a va_list instead of a
variable number of arguments. dm_logger_append is now a minimal wrapper
around dm_logger_append_va.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
o The h array had more entries than were emitted, all are now removed
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Fri, 1 Dec 2017 06:27:04 +0000 (01:27 -0500)]
drm/amd/display: remove usage of legacy_cursor_update
Currently the atomic check code uses legacy_cursor_update
to differnetiate if the cursor plane is being requested by
the user, which is not required as we shall be updating
plane only if modeset is requested/required.
Have tested cursor plane and underlay get updated seamlessly,
without any lag or frame drops.
Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Fri, 24 Nov 2017 04:31:36 +0000 (12:31 +0800)]
drm/amd/include:cleanup vega10 header files.
Remove asic_reg/vega10 folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Thu, 23 Nov 2017 07:02:23 +0000 (15:02 +0800)]
drm/amd/include:cleanup vega10 nbif header files.
Cleanup asic_reg/vega10/NBIF folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Thu, 23 Nov 2017 06:54:48 +0000 (14:54 +0800)]
drm/amd/include:cleanup vega10 nbio header files.
Cleanup asic_reg/vega10/NBIO folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Thu, 23 Nov 2017 06:08:34 +0000 (14:08 +0800)]
drm/amd/include:cleanup vega10 vce header files.
Cleanup asic_reg/vega10/VCE folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Wed, 22 Nov 2017 07:23:20 +0000 (15:23 +0800)]
drm/amd/include: cleanup vega10 umc header files.
Remove asic/vega10/UMC folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Wed, 22 Nov 2017 06:57:05 +0000 (14:57 +0800)]
drm/amd/include:cleanup vega10 thm header files.
Cleanup asic_reg/vega10/THM folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
To remove include/asic_reg/vega10 folder,create IP folders sdma0/1.
This patch cleanup asic_reg/vega10/SDMA folders.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Because after suspend VRAM will be cleared, so driver must
unpin the GART table(resident in VRAM) during suspend so it
can be evicted to system ram and must correspondingly pin it
during resume so the GART table could be restored to VRAM.
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger He [Tue, 21 Nov 2017 08:47:16 +0000 (16:47 +0800)]
drm/ttm: roundup the shrink request to prevent skip huge pool
e.g. shrink reqeust is less than 512, the logic will skip huge pool
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger He [Tue, 21 Nov 2017 06:24:48 +0000 (14:24 +0800)]
drm/ttm: add page order support in ttm_pages_put
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger He [Wed, 22 Nov 2017 07:09:33 +0000 (15:09 +0800)]
drm/ttm: add set_pages_wb for handling page order more than zero
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Wed, 15 Nov 2017 03:11:05 +0000 (22:11 -0500)]
drm/amd/display: dal 3.1.20
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrew Jiang [Tue, 14 Nov 2017 17:40:20 +0000 (12:40 -0500)]
drm/amd/display: Set OPP default values in init_hw
On S3 resume, we do not reconstruct OPP, but we do need to
reinitialize some of its values to the default ones.
Therefore, move those lines out of the OPP constructor and
into init_hw.
Also reset the hubp power gated flag, since nothing is
power gated at init_hw.
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Mon, 13 Nov 2017 23:49:33 +0000 (18:49 -0500)]
drm/amd/display: dal 3.1.19
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Mon, 13 Nov 2017 15:54:59 +0000 (10:54 -0500)]
drm/amd/display: DMCU and ABM maintenance and refactor
Remove some globals that should really be per block state.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Mon, 13 Nov 2017 22:22:17 +0000 (17:22 -0500)]
drm/amd/display: Only program watermark for full update.
For scaling and position change, it isn't necessary to program
watermark and check P-State as well.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Mon, 13 Nov 2017 23:02:57 +0000 (18:02 -0500)]
drm/amd/display: dal 3.1.18
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrew Jiang [Mon, 13 Nov 2017 22:09:12 +0000 (17:09 -0500)]
drm/amd/display: Set full update flag in dcn_validate_bandwidth
Doing bandwidth validation implies that this is a full update. Set the
flag inside the function in case whatever is calling
dcn_validate_bandwidth doesn't set it.
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Fri, 10 Nov 2017 21:12:08 +0000 (16:12 -0500)]
drm/amd/display: Do not program front-end twice
The sequence of front-end > back-end > front-end programming will
program the front-end more than once. Add a mode_changed flag, and use
it to determine whether the front-end should be programmed before, or
after back-end.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Trigger full update on plane change
With the optimized DCN10 frontend programming code, things are
programmed only when requested. For now, trigger a full update on all
plane changes.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
There was an error in translation of mode support check.
"N/A" is a failure condition while "" was a special case.
This change will differentiate between the two by using a
define.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yue Hin Lau [Mon, 13 Nov 2017 19:55:07 +0000 (14:55 -0500)]
drm/amd/display: move csc matrix to hw_shared
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Sat, 11 Nov 2017 04:23:24 +0000 (23:23 -0500)]
drm/amd/display: dal 3.1.17
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yue Hin Lau [Thu, 9 Nov 2017 22:03:00 +0000 (17:03 -0500)]
drm/amd/display: update output csc matrix values
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Fri, 10 Nov 2017 20:40:52 +0000 (15:40 -0500)]
drm/amd/display: Only update output transfer function for full type.
dcn10_translate_regamma_to_hw_format costs 750us to run, it cannot be
called within isr, check update flag before calling, only do it for
full update.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
None of this needs to be a function table or dynamic in any way.
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yue Hin Lau [Thu, 9 Nov 2017 20:56:25 +0000 (15:56 -0500)]
drm/amd/display: fix opp header register define
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Wed, 8 Nov 2017 22:24:54 +0000 (17:24 -0500)]
drm/amd/display: Update dchub and dpp as per update flags.
Check update flags and update dchub and dpp as per flags,
reduce reg access from 347 to 200, duration time reduce
to 170us.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Thu, 9 Nov 2017 18:55:46 +0000 (13:55 -0500)]
drm/amd/display: Move update_plane_addr to apply_ctx_for_surface for dce.
Move update_plane_addr to apply_ctx_for_surface, address update will
just be called once, not twice for updat type is full and medium.
This will reduce some reg access and duration time.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yue Hin Lau [Wed, 1 Nov 2017 20:48:52 +0000 (16:48 -0400)]
drm/amd/display: call set_mpc_output_csc from hwsequencer
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Wed, 22 Nov 2017 14:55:22 +0000 (15:55 +0100)]
drm/amd/display: Fix description of module parameter dc_log
It was incorrectly referencing the dc parameter, resulting in an empty
description of the dc_log parameter.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Wed, 22 Nov 2017 14:55:21 +0000 (15:55 +0100)]
drm/amdgpu: Downgrade DRM_ERROR to DRM_DEBUG in amdgpu_queue_mgr_map
Prevent buggy userspace from spamming dmesg.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 7 Nov 2017 11:03:31 +0000 (12:03 +0100)]
drm/amdgpu: expose the VA above the hole to userspace
Let userspace know how much area we have above the 48bit VA hole on
Vega10.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 13 Nov 2017 12:58:17 +0000 (13:58 +0100)]
drm/amdgpu: use dev_dbg instead of dev_err in the VA IOCTL
Userspace buggy userspace can spam the logs.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 6 Nov 2017 14:37:01 +0000 (15:37 +0100)]
drm/amdgpu: fix VA hole handling on Vega10 v3
Similar to the CPU address space the VA on Vega10 has a hole in it.
v2: use dev_dbg instead of dev_err
v3: add some more comments to explain how the hw works
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> CC: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 27 Apr 2017 16:20:47 +0000 (18:20 +0200)]
drm/amdgpu: use the new TTM bytes moved counter v2
Instead of the global statistics use the per context bytes moved counter.
v2: rebased
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 26 Apr 2017 14:44:41 +0000 (16:44 +0200)]
drm/amdgpu: forward operation context to ttm_bo_mem_space
This way we can finally use some more stats.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 24 Nov 2017 10:32:59 +0000 (11:32 +0100)]
staging: vboxvideo: adapt to new TTM interface
Fixes interface changes done in the following commits:
drm/ttm: add operation ctx to ttm_bo_validate v2
drm/ttm: add context to driver move callback as well
I missed this driver because it is in the staging area.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / kernel.git / log