Added Event Log driver support for DRTM. This driver
is responsible for the doing the hash measurement of
various DRTM components as per [1], and putting these
measurements in the Event Log buffer.
Manish Pandey [Mon, 20 Jun 2022 16:42:41 +0000 (17:42 +0100)]
feat(drtm): introduce drtm dynamic launch function
This function is placeholder for checking all the necessary conditions
before doing drtm dynamic launch.
In this patch following conditions are checked (based on Table 31 of
DRTM spec beta0), rest of the conditions will be added in later
patches.
- Only boot PE is online
- Caller execution state is AArch64
- Caller exception level is NS-EL2 or NS-EL1
refactor(measured-boot): split out a few Event Log driver functions
Reorganized a few Event Log functions into multiple functions so that
they can be used for the upcoming DRTM feature. This change mainly
implements below new functions -
1. event_log_buf_init - called by 'event_log_init' to initialise Event
Log buffer
2. event_log_write_specid_event - called by 'event_log_fixed_header' to
write specification id event to Event Log buffer
3. event_log_measure and event_log_record - called by
'event_log_measure_and_record' to measure and record the measurement
to the Event Log buffer
Change-Id: I1aabb57f79bead726fcf36d59839702cd6a3521d Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
John Powell [Thu, 12 May 2022 17:49:55 +0000 (12:49 -0500)]
feat(sdei): add a function to return total number of events registered
This patch adds a public API to return the total number of registered
events. The purpose of this is primarily for DRTM to ensure that no
SDEI event can interfere with a dynamic launch.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1d1cba2da7d5566cc340620ee1ce7d7844740b86
Updated DRTM setup functionality that mainly does below 2 things
1. Initialise the DRTM DMA protection, this function assumes the
platform must support complete DMA protection.
2. Initialise the Crypto module that will be useful to calculate
the hash of various DRTM element involved.
Added a dummy DRTM setup function and also, introduced DRTM SMCs
handling as per DRTM spec [1]. Few basic SMCs are handled in this
change such as ARM_DRTM_SVC_VERSION and ARM_DRTM_SVC_FEATURES
that returns DRTM version and functions ids supported respectively,
and others are dummy for now.
feat(fvp): add platform hooks for DRTM DMA protection
Added necessary platform hooks for DRTM DMA protection.
These calls will be used by the subsequent DRTM implementation
patches.
DRTM platform API declarations have been listed down in a
separate header file.
Andre Przywara [Tue, 4 Oct 2022 12:41:32 +0000 (13:41 +0100)]
fix(qemu): enable SVE and SME
Starting with QEMU v3.1.0 (Dec 2018), QEMU's TCG emulation engine supports
the SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained
SME support.
As it stands today, running TF-A under QEMU with "-cpu max" makes Linux
hang, because SME and SVE accesses trap to EL3, but are never handled
there. This is because the Linux kernel sees the SVE or SME feature bits,
and assumes firmware has enabled the feature for lower exception levels.
This requirement is described in the Linux kernel booting protocol.
Enable those features in the TF-A build, so that BL31 does the proper
EL3 setup to make the feature usable in non-secure world.
We check the actual feature bits before accessing SVE or SME registers,
so this is safe even for older QEMU version or when not running with
-cpu max. As SVE and SME are AArch64 features only, do not enable them
when building for AArch32.
Change-Id: I5b718eb298a0bbcf36244479e8d42e54a2faca61 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Edward-JW Yang [Mon, 5 Sep 2022 09:36:36 +0000 (17:36 +0800)]
feat(mt8188): add cpu_pm driver
- Add cpu_pm driver for CPU idle and SMP flow.
- Add SMP driver for CPU power on/off control.
- Add CPC driver to handle CPU powered on/off in CPU suspend.
- Add mbox driver for tinysys support.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I20141474e1c43cdfacb9f2c6a2285721e50a617c
Yann Gautier [Thu, 29 Aug 2019 17:04:29 +0000 (19:04 +0200)]
feat(stm32mp1): add plat_report_*_abort functions
The new helpers are created in STM32MP1 platform for prefetch and data
aborts.
While at it, put plat_report_exception() under DEBUG flag. If DEBUG is
not set, the weak function which does the same will be used.
This plat_report_exception() function can also be simplified, as it will
no more be used to report aborts.
Yann Gautier [Fri, 15 Feb 2019 15:42:20 +0000 (16:42 +0100)]
feat(debug): add helpers for aborts on AARCH32
New helper functions are created to handle data & prefetch aborts
in AARCH32. They call platform functions, just like what
report_exception is doing.
As extended MSR/MRS instructions (to access lr_abt in monitor mode)
are only available if CPU (Armv7) has virtualization extension,
the functions branch to original report_exception handlers if this is
not the case.
Those new helpers are created mainly to distinguish data and prefetch
aborts, as they both share the same mode.
This adds 40 bytes of code.
Michal Simek [Mon, 3 Oct 2022 12:02:57 +0000 (14:02 +0200)]
fix(versal-net): use api_id directly without FUNCID_MASK
The purpose of this code is to extract api_id from smc_fid but this masking
is done already in the code with using generic mask from smccc.h
(FUNCID_NUM_MASK). That's why remove FUNCID_MASK is which not needed and
actually also equal to already used FUNCID_NUM_MASK.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I1113825baa5d9d58d9d7c5d9d5855fecf62e8d45
On one hand, there is currently no upstream platform supporting the
RSS. On the other hand, we are gradually introducing driver code for
RSS. Even though we cannot test this code in the TF-A CI right now, we
can at least build it to make sure no build regressions are introduced
as we continue development.
This patch adds support for overriding PLAT_RSS_NOT_SUPPORTED build
flag (which defaults to 1 on the Base AEM FVP) from the command
line. This allows introducing an ad-hoc CI build config with
PLAT_RSS_NOT_SUPPORTED=0, which will correctly pull in the RSS and MHU
source files. Of course, the resulting firmware will not be
functional.
Joel Goddard [Wed, 21 Sep 2022 16:22:28 +0000 (21:52 +0530)]
refactor(cpu): use the updated IP name for Demeter CPU
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the updated IP name.
Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f
Manish Pandey [Mon, 3 Oct 2022 09:58:07 +0000 (11:58 +0200)]
Merge changes from topic "st_uart_updates" into integration
* changes:
feat(stm32mp1): add early console in SP_min
feat(st): properly manage early console
feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
feat(st): add trace for early console
fix(stm32mp1): enable crash console in FIQ handler
feat(st-uart): add initialization with the device tree
refactor(stm32mp1): move DT_UART_COMPAT in include file
feat(stm32mp1): configure the serial boot load address
fix(stm32mp1): update the FIP load address for serial boot
refactor(st): configure baudrate for UART programmer
refactor(st-uart): compute the over sampling dynamically
According to the Generic Names Recommendation in the Devicetree
Specification Release v0.3, and the DT Bindings for the Renesas Reduced
Pin Count Interface, the node name for a Renesas RPC-IF device should be
"spi". The node name matters, as the node is enabled by passing a DT
fragment from TF-A to subsequent software.
Fix this by renaming the device node in the passed DT fragment from
"rpc" to "spi".
Fixes: 12c75c8886a0ee69 ("feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Change-Id: Idb43353947607611331abc344f8c8ae932a20408
Yann Gautier [Mon, 3 Oct 2022 07:30:34 +0000 (09:30 +0200)]
fix(st): add missing string.h include
Since patch on libc refactoring, there is a compilation error with
STM32MP_USB_PROGRAMMER=1:
plat/st/common/stm32cubeprogrammer_usb.c:81:35: error:
implicit declaration of function 'strnlen'
[-Werror=implicit-function-declaration]
length += strnlen((char *)&dfu->buffer[GET_PHASE_LEN],
refactor(psci): unify psci_is_last_on_cpu and psci_is_last_on_cpu_safe
"psci_is_last_on_cpu" and "psci_is_last_on_cpu_safe" modules perform
mostly similar functionalities, verifying whether the current CPU
is the only active core and other cores have been turned off.
However, psci_is_last_on_cpu_safe function differs from the other with:
1. Safe API locks the power domain
This patch removes the section duplicating the functionality
and ensures that "psci_is_last_on_cpu api",is reused in
"psci_is_last_on_cpu_safe" procedure.
fix(ras): trap "RAS error record" accesses only for NS
RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error
record registers (RAS ERR* & RAS ERX*) from lower EL's in any security
state. To give more fine grain control per world basis re-purpose this
macro to RAS_TRAP_NS_ERR_REC_ACCESS, which will enable the trap only
if Error record registers are accessed from NS.
This will also help in future scenarios when RAS handling(in Firmware
first handling paradigm)can be offloaded to a secure partition.
This is first patch in series to refactor RAS framework in TF-A.
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.
Raef Coles [Wed, 15 Jun 2022 13:37:22 +0000 (14:37 +0100)]
feat(rss): add new comms protocols
The current comms protocol (where arguments and return data is embedded
into the MHU message) is now protocol v0. Protocol v1 embeds pointers
into the message, and has the RSS retrieve the data via DMA.
Change-Id: I08d7f09c4eaea673769fde9eee194447a99f1b78 Signed-off-by: Raef Coles <raef.coles@arm.com>
feat(ls1043ardb): update ddr configure for ls1043ardb-pd
DDR4 Chip is EOL during redesign of ls1043ardb pd version. The replacement from MT is MT40A1G8SA-062E:R.
New ddr configure is compatible with both pd and old version of ls1043ardb.
This fix solves problems with using PRI*PTR on aarch64 like so:
error: format '%x' expects argument of type 'unsigned int', but
argument 3 has type 'uintptr_t' {aka 'long unsigned int'}
Change-Id: I135d3e5cea5459f138b20331b5e9472e2e9e566c Signed-off-by: K <kayo@illumium.org>
The new flag STM32MP_RECONFIGURE_CONSOLE is managed in platform.mk.
It is used in stm32mp_setup_early_console() when calling
plat_crash_console_init(). This call is also under:
"#if defined(IMAGE_BL2)"
as this crash console init shouldn't be done by default in BL32.
If the flag STM32MP_RECONFIGURE_CONSOLE is set in BL32, the UART init
should be skipped if the UART clock is set to zero. This will be used
when configuring the default console, after an early console has been
configured.
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured in BL2.
Yann Gautier [Mon, 7 Mar 2022 15:09:23 +0000 (16:09 +0100)]
fix(stm32mp1): enable crash console in FIQ handler
When a FIQ occurs and is trapped by SP_min, it is an unrecoverable
error. As kernel may have switched the UART console off, we should
re-enable it with plat_crash_console_init() for those failing states.
Patrick Delaunay [Thu, 14 Apr 2022 09:19:03 +0000 (11:19 +0200)]
feat(st-uart): add initialization with the device tree
Add the pincontrol configuration and clock enable in UART driver
with information found in the device tree.
This patch avoids an issue on STM32MP13x platform because the UART
configuration is reset by the ROM code for UART serial boot
(STM32MP_UART_PROGRAMMER=1).
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I575fd0e1026b857059abcfd4a3166eb3a239e1fd
Patrick Delaunay [Tue, 15 Mar 2022 10:20:56 +0000 (11:20 +0100)]
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
Patrick Delaunay [Mon, 28 Feb 2022 10:02:35 +0000 (11:02 +0100)]
fix(stm32mp1): update the FIP load address for serial boot
Update the FIP load address and size for serial boot to support
product with a DDR size = 128MB
1/ Move the FIP location at the end of the first 128MB
2/ Reduce the DWL_BUFFER_SIZE to 16MB, to be coherent with the value
indicated in USB enumeration
- for STM32MP13x: "@SSBL /0x03/1*16Me"
- for STM32MP15x: "@Partition3 /0x03/1*16Me"
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id93bf00c64832c17426bfd78e060861275677ecc
refactor(st-uart): compute the over sampling dynamically
The parameter over_sampling of stm32_uart_init_s is not required
as it can be computed dynamically from clock rate of the serial
device and the requested baudrate.
Oversampling by 8 is allowed only for higher speed
(up to clock_rate / 8) to reduce the maximum receiver tolerance
to clock deviation.
This patch update the driver, the serial init struct and the
only user, the stm32cubeprogrammer over uart support.
Change-Id: I422731089730a288defeb7fa49886db65d0902b2 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
feat(sgi): remove override for `ARM_BL31_IN_DRAM` build-option
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
within the common makefile would deter these platforms from having this
flexibility. Remove the default override configuration for
`ARM_BL31_IN_DRAM`.
feat(sgi): configure SRAM and BL31 size for sgi platform
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-chip SRAM. Additionally, revise BL31 image size to accommodate
larger BL31 images of multi-chip platforms.
Merge changes from topic "mediatek upstream" into integration
* changes:
refactor(mt8188): move platform_def.h to mt8188/include
feat(mt8188): add MCUSYS support
feat(mt8188): add armv8.2 support
feat(mt8188): add DFD control in SiP service
feat(mt8188): add EMI MPU basic drivers
feat(mt8188): add DCM driver
feat(mt8188): add reset and poweroff functions
feat(mediatek): add more flexibility of mtk_pm.c
feat(mediatek): add more options for build helper
feat(mt8188): add LPM driver support
feat(mt8188): apply ERRATA for CA-78
fix(mediatek): remove unused cold_boot.[c|h]
fix(mediatek): wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE
feat(mt8186): add EMI MPU support for SCP and DSP
projects / arm-tf.git / log