Ben Skeggs [Sun, 6 Dec 2020 02:14:13 +0000 (12:14 +1000)]
drm/nouveau/nvkm: add macros for subdev layout
Rather than having to add new engines / engine instances to multiple places,
define everything in include/nvkm/core/layout.h and use macros to generate
the required plumbing.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
We use subdev id bitmasks (as a u64) in a number of places, and GA100 adds
enough new engine instances that we run out of bits. We could alias IDs of
engines that no longer exist, but it's cleaner for a number of reasons to
just split the subdev index into a subdev type, and instance ID instead.
Just a lot more painful to do.
This magics up the values for old-style subdev constructors, and provides a
way to incrementally transition each subdev to the new style.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
Ben Skeggs [Wed, 2 Dec 2020 05:52:46 +0000 (15:52 +1000)]
drm/nouveau/subdev: remove nvkm_subdev.mutex
There's not really any nice way to assign the lock classes when we split
subdev indices into type+inst, and saves a few bytes in the structs when
a subdev has no need for it.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
Dave Airlie [Thu, 4 Feb 2021 23:38:19 +0000 (09:38 +1000)]
Merge tag 'amd-drm-next-5.12-2021-02-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.12-2021-02-03:
amdgpu:
- Display fixes and cleanups
- Vangogh fixes
- Fix possible race when there are timeouts on two rings
- SR-IOV fixes
- Add missing license
- DCE 10/12 bpc fixes
- Display MALL fixes
- Fix SMU user preference settings persistence
- Fix retry in gem allocate
- Add new PCI DID
- Fix for manual fan speed control on cards where it was problematic
- Fix regression in pinning GTT
- Misc display fixes
- Misc code cleanups
Yongqiang Niu [Tue, 2 Feb 2021 08:12:35 +0000 (16:12 +0800)]
drm/mediatek: Add matrix_bits private data for ccorr
Add matrix_bits and coeffs_precision to ccorr private data:
- matrix bits of mt8183 is 10
- matrix bits of mt8192 is 11
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Tue, 2 Feb 2021 08:12:34 +0000 (16:12 +0800)]
drm/mediatek: Fix ccorr size config
Fix setting to follow hardware datasheet. The original error setting
affects mt8192 display.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Tue, 2 Feb 2021 08:12:33 +0000 (16:12 +0800)]
drm/mediatek: Separate ccorr module
ccorr ctm matrix bits will be different in mt8192.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Fri, 29 Jan 2021 07:34:32 +0000 (15:34 +0800)]
drm/mediatek: Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
ovl will hang up when more than 1 layer enabled.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Fri, 29 Jan 2021 09:22:09 +0000 (17:22 +0800)]
drm/mediatek: Add support for SoC MT8183
1. Add ovl private data
2. Add rdma private data
3. Add gamma privte data
4. Add main and external path module for crtc create
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Fri, 29 Jan 2021 09:22:06 +0000 (17:22 +0800)]
drm/mediatek: Add has_dither private data for gamma
Not all SoC has dither function in gamma module.
Add private data to control this function setting.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Fri, 29 Jan 2021 09:22:05 +0000 (17:22 +0800)]
drm/mediatek: Separate gamma module
mt8183 gamma module will different with mt8173,
so separate gamma for adding private data.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Hsin-Yi Wang [Fri, 29 Jan 2021 09:22:04 +0000 (17:22 +0800)]
drm/mediatek: Add mtk_dither_set_common() function
Current implementation of mtk_dither_set() cast dev data to
struct mtk_ddp_comp_dev. But other devices with different dev data
would also call this function.
Separate necessary parameters out so other device components (dither,
gamma) can call this function.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Mon, 11 Jan 2021 07:43:47 +0000 (15:43 +0800)]
drm/mediatek: Fix aal size config
The orginal setting is not correct, fix it to follow hardware data sheet.
If keep this error setting, mt8173/mt8183 display ok
but mt8192 display abnormal.
Hsin-Yi Wang [Thu, 3 Dec 2020 08:24:45 +0000 (16:24 +0800)]
drm/mediatek: mtk_dpi: Create connector for bridges
Similar to commit c8516d4f090a
("drm/mediatek: mtk_dsi: Create connector for bridges"):
Use the drm_bridge_connector helper to create a connector for pipelines
that use drm_bridge. This allows splitting connector operations across
multiple bridges when necessary, instead of having the last bridge in
the chain creating the connector and handling all connector operations
internally.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Yongqiang Niu [Mon, 11 Jan 2021 07:43:44 +0000 (15:43 +0800)]
drm/mediatek: Check if fb is null
It's possible that state->base.fb is null. Add a check before access its
format.
Fixes: 51be20ef4508 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Dave Airlie [Thu, 4 Feb 2021 02:57:18 +0000 (12:57 +1000)]
Merge tag 'drm-intel-next-2021-01-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- WARN if plane src coords are too big (Ville)
- Prevent double YUV range correction on HDR planes (Andres)
- DP MST related Fixes (Sean, Imre)
- More clean-up around DRAM detection code (Jose)
- Actually async flips enable for all ilk+ platforms (Ville)
Dave Airlie [Thu, 4 Feb 2021 02:31:16 +0000 (12:31 +1000)]
Merge tag 'drm/tegra/for-5.12-rc1' of ssh://git.freedesktop.org/git/tegra/linux into drm-next
drm/tegra: Changes for v5.12-rc1
Adds support for newer firmware image versions of the Video Image
Composer (VIC) and adds a comment clarifying the use of the STREAMID
registers. Fixes a couple of issues with display and gr2d on older
Tegra SoCs such as Tegra114, as well as a runtime PM reference leak.
Dan Carpenter [Tue, 2 Feb 2021 05:56:36 +0000 (08:56 +0300)]
drm/amdgpu: Prevent shift wrapping in amdgpu_read_mask()
If the user passes a "level" value which is higher than 31 then that
leads to shift wrapping. The undefined behavior will lead to a
syzkaller stack dump.
Fixes: c69bad879d91 ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 25 Jan 2021 04:14:54 +0000 (23:14 -0500)]
drm/amd/display: 3.2.121
This version brings along following fixes:
- Better handling of dummy p-state table
- Workaround for some legacy DP-VGA dongles
- Add Freesync HDMI support to DMCU
- Enable "trigger_hotplug" debugfs on all outputs
- fix initial bounding box values for dcn3.02
- implement support for DID2.0 dsc passthrough
- fix calculation for the pwl backlight curve
- Fix multiple memory leaks
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 23 Jan 2021 21:28:21 +0000 (16:28 -0500)]
drm/amd/display: [FW Promotion] Release 0.0.50
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Fri, 22 Jan 2021 03:35:54 +0000 (22:35 -0500)]
drm/amd/display: Reject too small viewport size when validating plane
[why]
Overlay won't move to a new positon if viewport size is smaller than
what can be handled. It'd either disappear or stay at the old
position. This condition is for example hit if overlay is moved too
much outside of left or top edge of the screen, but it applies to
any non-cursor plane type.
[how]
Reject this contidion at validation time. This gives the calling
level a chance to handle this gracefully and avoid inconsistent
behaivor.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Thu, 21 Jan 2021 07:33:31 +0000 (02:33 -0500)]
drm/amd/display: Better handling of dummy p-state table
[Why]
Some scenarios where we use a UCLK frequency in between dummy p-state table
entries result in a p-state hang, due to the table not having a close
enough match, so the default DPM0 latency is used, which can be too long to
support dummy p-state switching in these scenarios.
[How]
- old: match if current freq is within +- margin of table entry
- new: find largest table entry that is lower than current freq + margin
- lower than DPM0 will still use DPM0
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Fri, 15 Jan 2021 22:34:34 +0000 (17:34 -0500)]
drm/amd/display: Workaround for some legacy DP-VGA dongles
[Why]
Maximum resolution is 1440*900 when connecting to FHD monitor via some DP-VGA
dongles. The display EDID reading fails over AUX/I2C via DP->VGA dongle, and
this leads to the maximum resolution 1920*1080 cannot be obtained from EDID.
[How]
Provide a workaround for some legacy DP-VGA dongles with a longer aux delay.
Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Lu [Fri, 15 Jan 2021 16:02:48 +0000 (11:02 -0500)]
drm/amd/display: Decrement refcount of dc_sink before reassignment
[why]
An old dc_sink state is causing a memory leak because it is missing a
dc_sink_release before a new dc_sink is assigned back to
aconnector->dc_sink.
[how]
Decrement the dc_sink refcount before reassigning it to a new dc_sink.
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Lu [Thu, 14 Jan 2021 21:27:07 +0000 (16:27 -0500)]
drm/amd/display: Free atomic state after drm_atomic_commit
[why]
drm_atomic_commit was changed so that the caller must free their
drm_atomic_state reference on successes.
[how]
Add drm_atomic_commit_put after drm_atomic_commit call in
dm_force_atomic_commit.
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Remove force_ignore_link_settings debug option as it is no longer used.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stylon Wang [Fri, 4 Dec 2020 04:08:31 +0000 (12:08 +0800)]
drm/amd/display: Add Freesync HDMI support to DMCU
[Why]
Adding support for Freesync HDMI to DC and DMCU
[How]
Create DC interface and implementation on top of DMCU to support
parsing CEA blocks in DMCU.
Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stylon Wang [Tue, 29 Dec 2020 04:51:27 +0000 (12:51 +0800)]
drm/amd/display: Enable "trigger_hotplug" debugfs on all outputs
[Why]
Per-connector debugfs entry "trigger_hotplug" is available on DP/eDP only.
New IGT tests need this entry to test other outputs.
[How]
Enable this debugfs entry on all types of connectors
Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix CW4 programming for dmub30 cached inbox
[Why]
The conditions for whether we used cached vs non-cached inbox1 depend
on a version check that mismatches what the shared helpers in dmub20
implement.
[How]
Use the dmub_dcn20_use_cached_inbox check for dmub_dcn30 as well.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Tue, 12 Jan 2021 16:27:05 +0000 (11:27 -0500)]
drm/amd/display: fix initial bounding box values for dcn3.02
[Why]
Initial bounding box values are updated in dcn30_update_bw_bounding_box
but they use dcn3_0_soc and dcn3_0_ip instead of dcn3_02_soc and
dcn3_02_ip
[How]
Add dcn302_update_bw_bounding_box and
dcn302_get_optimal_dcfclk_fclk_for_uclk so it uses
dcn3_02_soc and dcn3_02_ip.
Use sr_exit_time_us, sr_enter_plus_exit_time_us,
from dcn30 on dcn302 to fix flicker on eDP.
Also use dram_clock_change_latency_us from dcn30.
Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Wed, 16 Dec 2020 17:56:38 +0000 (12:56 -0500)]
drm/amd/display: implement support for DID2.0 dsc passthrough
[Why]
Some panels contain active converters (e.g. DP to MIPI) which only support
restricted DSC configurations. DID2.0 adds support for such displays to
explicitly define per timing BPP restrictions on DSC. Ignoring these
restrictions leads to blackscreen.
[How]
Add parsing in DID2.0 parser to get this bpp info.
Add support in DSC module to constraint target bpp based
on this info.
Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Lu [Fri, 15 Jan 2021 03:24:14 +0000 (22:24 -0500)]
drm/amd/display: Fix dc_sink kref count in emulated_link_detect
[why]
prev_sink is not used anywhere else in the function and the reference to
it from dc_link is replaced with a new dc_sink.
[how]
Change dc_sink_retain(prev_sink) to dc_sink_release(prev_sink).
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Thu, 14 Jan 2021 16:48:57 +0000 (11:48 -0500)]
drm/amd/display: Release DSC before acquiring
[why]
Need to unassign DSC from pipes that are not using it
so other pipes can acquire it. That is needed for
asic's that have unmatching number of DSC engines from
the number of pipes.
[how]
Before acquiring dsc to stream resources, first remove it.
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Eryk Brol <Eryk.Brol@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / kernel.git / log