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7 years agodrm/i915/gvt/kvmgt: fill info for ROM/VGA region
Pei Zhang [Fri, 8 Dec 2017 07:31:12 +0000 (15:31 +0800)]
drm/i915/gvt/kvmgt: fill info for ROM/VGA region

Both ROM/VGA region are not supported for vGPU in GVT. But if the device
model want to get those region, we should return the correct information
but not leave the structure with random data. Change to same operation
of BAR3-BAR5 which are also not supported by vGPU.

Refer to function @intel_vgpu_rw.

Signed-off-by: Pei Zhang <pei.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Rename file render.{c, h} to mmio_context.{c, h}
Changbin Du [Fri, 8 Dec 2017 06:56:23 +0000 (14:56 +0800)]
drm/i915/gvt: Rename file render.{c, h} to mmio_context.{c, h}

Rename the files to reflect their real role - to switch the mmio context of
each vGPU engine.

v2: update Makefile.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Remove MMIO barrier in MMIO switch
Changbin Du [Fri, 8 Dec 2017 06:56:22 +0000 (14:56 +0800)]
drm/i915/gvt: Remove MMIO barrier in MMIO switch

After engine mmio switched, software still need write workload
submission registers. So we can remove the MMIO barriar in MMIO
switch.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Select appropriate mmio list at initialization time
Changbin Du [Fri, 8 Dec 2017 06:56:21 +0000 (14:56 +0800)]
drm/i915/gvt: Select appropriate mmio list at initialization time

Select appropriate mmio list at initialization time, so we don't need to
do duplicated work at where requires the mmio list.

V2:
  - Add a termination mark of mmio list.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Refine the ring mmio list definition
Changbin Du [Fri, 8 Dec 2017 06:56:20 +0000 (14:56 +0800)]
drm/i915/gvt: Refine the ring mmio list definition

To improve the readability, let's remove the hard code for each mmio
definition. The raw offset remained as a comment, which give us an
offset based view.

This refine is to make it convenient for new platform enabling.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: fix off-by-one comparison of ring_id
Colin Ian King [Mon, 4 Dec 2017 17:21:06 +0000 (17:21 +0000)]
drm/i915/gvt: fix off-by-one comparison of ring_id

The ring_id maximum boundary is being compared using the > operator
instead of >=, leading to an off-by-one error and an out of bounds
write into array vgpu->hws_pga[].  Fix this by simply using the
correct comparison operator. Also re-work another comparison that
uses the comparison > I915_NUM_ENGINES - 1 to use the >= idiom using
to keep this consistent in this code.

Detected by CoverityScan, CID#1462404 ("Out-of-bounds write")

Fixes: a2ae95af9646 ("drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add missing breaks in switch statement
Colin Ian King [Mon, 4 Dec 2017 16:48:18 +0000 (16:48 +0000)]
drm/i915/gvt: Add missing breaks in switch statement

The switch statement is missing breaks for the cases of
GVT_FAILSAFE_INSUFFICIENT_RESOURCE and GVT_FAILSAFE_GUEST_ERR. Add them
in.

Detected by CoverityScan, CID#1462416 ("Missing break in switch")

Fixes: e011c6ce2b4f ("drm/i915/gvt: Add VM healthy check for workload_thread")
Fixes: a33fc7a0482a ("drm/i915/gvt: enter failsafe mode when guest requires more resources")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: set max priority for gvt context
Zhenyu Wang [Mon, 4 Dec 2017 02:42:58 +0000 (10:42 +0800)]
drm/i915/gvt: set max priority for gvt context

This is to workaround guest driver hang regression after
preemption enable that gvt hasn't enabled handling of that
for guest workload. So in effect this disables preemption
for gvt context now.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Don't mark vgpu context as inactive when preempted
Zhenyu Wang [Fri, 1 Dec 2017 06:59:53 +0000 (14:59 +0800)]
drm/i915/gvt: Don't mark vgpu context as inactive when preempted

We shouldn't mark inactive for vGPU context if preempted,
which would still be re-scheduled later. So keep active state.

Fixes: d6c0511300dc ("drm/i915/execlists: Distinguish the incomplete context notifies")
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Kick scheduler when new workload queued
Changbin Du [Wed, 29 Nov 2017 07:40:07 +0000 (15:40 +0800)]
drm/i915/gvt: Kick scheduler when new workload queued

The current schedule policy rely on a 1ms timer to execute workload. This
can introduce maximum 1ms unnecessary latency. This is especially bad for
small media workloads.

And I don't think we need this timer for QoS, but the change is not simply
remove the code. So I made a new API intel_gvt_kick_schedule() for future
change.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Convert macro queue_workload to a function
Changbin Du [Wed, 29 Nov 2017 07:40:06 +0000 (15:40 +0800)]
drm/i915/gvt: Convert macro queue_workload to a function

Convert the macro to a function which should always be preferred.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Free dmabuf_obj list in intel_vgpu_dmabuf_cleanup
Tina Zhang [Wed, 29 Nov 2017 06:57:37 +0000 (14:57 +0800)]
drm/i915/gvt: Free dmabuf_obj list in intel_vgpu_dmabuf_cleanup

The per vGPU dmabuf_obj list should be released in intel_vgpu_dmabuf_
cleanup, which is invoked either in the process of closing a VM or in
the process of removing a vGPU.

Fixes: e3a0d7976c53 ("drm/i915/gvt: Handle orphan dmabuf_objs")
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Introduce KBL to dma-buf on Gvt-g
Tina Zhang [Tue, 28 Nov 2017 05:50:42 +0000 (13:50 +0800)]
drm/i915/gvt: Introduce KBL to dma-buf on Gvt-g

This patch introduces KBL platform to dma-buf on Gvt-g.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Handle orphan dmabuf_objs
Tina Zhang [Thu, 23 Nov 2017 08:26:37 +0000 (16:26 +0800)]
drm/i915/gvt: Handle orphan dmabuf_objs

dmabuf_obj's destruction relys on GEM release operation, which is managed
in i915 driver. And there is a time window between vgpu's destruction and
its dmabuf_objs' destruction. This patch is to free the orphan dmabuf_objs
correctly after the vgpu passes away.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Dmabuf support for GVT-g
Tina Zhang [Thu, 23 Nov 2017 08:26:36 +0000 (16:26 +0800)]
drm/i915/gvt: Dmabuf support for GVT-g

This patch introduces a guest's framebuffer sharing mechanism based on
dma-buf subsystem. With this sharing mechanism, guest's framebuffer can
be shared between guest VM and host.

v17:
- modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex)

v16:
- add x_hot and y_hot. (Gerd)
- add flag validation for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)
- rebase 4.14.0-rc6.

v15:
- add VFIO_DEVICE_GET_GFX_DMABUF ABI. (Gerd)
- add intel_vgpu_dmabuf_cleanup() to clean up the vGPU's dmabuf. (Gerd)

v14:
- add PROBE, DMABUF and REGION flags. (Alex)

v12:
- refine the lifecycle of dmabuf.

v9:
- remove dma-buf management. (Alex)
- track the dma-buf create and release in kernel mode. (Gerd) (Daniel)

v8:
- refine the dma-buf ioctl definition.(Alex)
- add a lock to protect the dmabuf list. (Alex)

v7:
- release dma-buf related allocations in dma-buf's associated release
  function. (Alex)
- refine ioctl interface for querying plane info or create dma-buf.
  (Alex)

v6:
- align the dma-buf life cycle with the vfio device. (Alex)
- add the dma-buf related operations in a separate patch. (Gerd)
- i915 related changes. (Chris)

v5:
- fix bug while checking whether the gem obj is gvt's dma-buf when user
  change caching mode or domains. Add a helper function to do it.
  (Xiaoguang)
- add definition for the query plane and create dma-buf. (Xiaoguang)

v4:
- fix bug while checking whether the gem obj is gvt's dma-buf when set
  caching mode or doamins. (Xiaoguang)

v3:
- declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
  to represent the gem obj for gvt's dma-buf. The tiling mode, caching
  mode and domains can not be changed for this kind of gem object. (Alex)
- change dma-buf related information to be more generic. So other vendor
  can use the same interface. (Alex)

v2:
- create a management fd for dma-buf operations. (Alex)
- alloc gem object's backing storage in gem obj's get_pages() callback.
  (Chris)

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agovfio: ABI for mdev display dma-buf operation
Tina Zhang [Thu, 23 Nov 2017 08:26:35 +0000 (16:26 +0800)]
vfio: ABI for mdev display dma-buf operation

Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user query and get
a plane and its information. So far, two types of buffers are supported:
buffers based on dma-buf and buffers based on region.

This ioctl can be invoked with:
1) Either DMABUF or REGION flag. Vendor driver returns a plane_info
successfully only when the specific kind of buffer is supported.
2) Flag PROBE. And at the same time either DMABUF or REGION must be set,
so that vendor driver returns success only when the specific kind of
buffer is supported.

Add VFIO_DEVICE_GET_GFX_DMABUF ioctl command to let user get a specific
dma-buf fd of an exposed MDEV buffer provided by dmabuf_id which was
returned in VFIO_DEVICE_QUERY_GFX_PLANE ioctl command.

The life cycle of an exposed MDEV buffer is handled by userspace and
tracked by kernel space. The returned dmabuf_id in struct vfio_device_
query_gfx_plane can be a new id of a new exposed buffer or an old id of
a re-exported buffer. Host user can check the value of dmabuf_id to see
if it needs to create new resources according to the new exposed buffer
or just re-use the existing resource related to the old buffer.

v18:
- update comments for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)

v17:
- modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex)

v16:
- add x_hot and y_hot fields. (Gerd)
- add comments for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)
- rebase to 4.14.0-rc6.

v15:
- add a ioctl to get a dmabuf for a given dmabuf id. (Gerd)

v14:
- add PROBE, DMABUF and REGION flags. (Alex)

v12:
- add drm_format_mod back. (Gerd and Zhenyu)
- add region_index. (Gerd)

v11:
- rename plane_type to drm_plane_type. (Gerd)
- move fields of vfio_device_query_gfx_plane to vfio_device_gfx_plane_info.
  (Gerd)
- remove drm_format_mod, start fields. (Daniel)
- remove plane_id.

v10:
- refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE. (Alex) (Gerd)

v3:
- add a field gvt_plane_info in the drm_i915_gem_obj structure to save
  the decoded plane information to avoid look up while need the plane
  info. (Gerd)

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Kirti Wankhede <kwankhede@nvidia.com>
Acked-by: Alex Williamson <alex.williamson@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add framebuffer decoder support
Tina Zhang [Thu, 23 Nov 2017 08:26:32 +0000 (16:26 +0800)]
drm/i915/gvt: Add framebuffer decoder support

This patch is to introduce the framebuffer decoder which can decode guest
OS's framebuffer information, including primary, cursor and sprite plane.

v16:
- rebase to 4.14.0-rc6.

v14:
- refine pixel format table. (Zhenyu)

v9:
- move drm format change to a separate patch. (Xiaoguang)

v8:
- fix a bug in decoding primary plane. (Tina)

v7:
- refine framebuffer decoder code. (Zhenyu)

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add opregion support
Tina Zhang [Mon, 20 Nov 2017 07:31:16 +0000 (15:31 +0800)]
drm/i915/gvt: Add opregion support

Windows guest driver needs vbt in opregion, to configure the setting
for display. Without opregion support, the display registers won't
be set and this blocks display model to get the correct information
of the guest display plane.

This patch is to provide a virtual opregion for guest. The original
author of this patch is Xiaoguang Chen.

This patch is split from the "Dma-buf support for GVT-g" patch set,
with being rebased to the latest gvt-staging branch.

v3:
- add checking region index during intel_vgpu_rw. (Xiong)

v2:
- refine intel_vgpu_reg_release_opregion. (Xiong)

Here are the previous version comments:

v18:
- unmap vgpu's opregion when destroying vgpu.

v16:
- rebase to 4.14.0-rc6.

Signed-off-by: Bing Niu <bing.niu@intel.com>
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Tested-by: Xiong Zhang <xiong.y.zhang@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Alloc and Init guest opregion at vgpu creation
Xiong Zhang [Mon, 20 Nov 2017 07:31:15 +0000 (15:31 +0800)]
drm/i915/gvt: Alloc and Init guest opregion at vgpu creation

Currently guest opregion is allocated and initialised when guest
write opregion base register. This is too late for kvmgt, so
move it to vgpu_create time.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Tested-by: Tina Zhang <tina.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Fix out-of-bounds buffer write into opregion->signature[]
Chris Wilson [Mon, 4 Dec 2017 03:23:44 +0000 (11:23 +0800)]
drm/i915/gvt: Fix out-of-bounds buffer write into opregion->signature[]

sparse spots

drivers/gpu/drm/i915/gvt/opregion.c:234 alloc_and_init_virt_opregion() error: memcpy() 'header->signature' too small (16 vs 17)

as gvt is indeed trying to memcpy a string longer than the signature[].

Fixes: b2d6ef70614e ("drm/i915/gvt: Let each vgpu has separate opregion memory")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Xiong Zhang <xiong.y.zhang@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Cleanup unwanted public symbols
Chris Wilson [Mon, 20 Nov 2017 13:29:58 +0000 (13:29 +0000)]
drm/i915/gvt: Cleanup unwanted public symbols

drivers/gpu/drm/i915/gvt/execlist.c:531:6: warning: symbol 'clean_execlist' was not declared. Should it be static?
drivers/gpu/drm/i915/gvt/execlist.c:545:6: warning: symbol 'reset_execlist' was not declared. Should it be static?
drivers/gpu/drm/i915/gvt/execlist.c:556:5: warning: symbol 'init_execlist' was not declared. Should it be static?
drivers/gpu/drm/i915/gvt/scheduler.c:248:6: warning: symbol 'release_shadow_wa_ctx' was not declared. Should it be static?

References: 06bb372f9ace ("drm/i915/gvt: Introduce intel_vgpu_reset_submission")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Move request alloc to dispatch_workload path only
fred gao [Tue, 14 Nov 2017 09:09:35 +0000 (17:09 +0800)]
drm/i915/gvt: Move request alloc to dispatch_workload path only

Previously the performance is improved through the workload auditing
and shadowing ahead of vGPU scheduling, however, there is the case that
more requests are allocated in submit_context before the previous request
is added, the timeline will hold its seqno which is later.

This patch is to move the request alloc to dispatch_workload function,
where is the same place as request is added.

It will fix the issue of kernel BUG for (timeline->seqno != request->fence.seqno)
check when add_request.

Fixes: 89ea20b930cb ("drm/i915/gvt: Factor out scan and shadow from workload dispatch")
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Let each vgpu has separate opregion memory
Xiong Zhang [Tue, 7 Nov 2017 16:45:21 +0000 (00:45 +0800)]
drm/i915/gvt: Let each vgpu has separate opregion memory

Currently every vgpu share a common gvt opregion memory, but
it is freed at vgpu destroy, then the later vgpu doesn't have
opregion memory once the first vgpu is destroyed. This cause
guest function failure like reboot, second or later boot.

This patch allocate and init virt opregion memory for each
vgpu, so this memory could be freed at vgpu destroy.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Limit read hw reg to active vgpu
Xiong Zhang [Mon, 6 Nov 2017 21:23:02 +0000 (05:23 +0800)]
drm/i915/gvt: Limit read hw reg to active vgpu

mmio_read_from_hw() let vgpu could read hw reg, if vgpu's workload
is running on hw, things is good. Otherwise vgpu will get other
vgpu's reg val, it is unsafe.

This patch limit such hw access to active vgpu. If vgpu isn't
running on hw, the reg read of this vgpu will get the last active
val which saved at schedule_out.

v2: ring timestamp is walking continuously even if the ring is idle.
    so read hw directly. (Zhenyu)

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agoRevert "drm/i915/gvt: Refine broken PPGTT scratch"
Zhenyu Wang [Thu, 2 Nov 2017 09:44:52 +0000 (17:44 +0800)]
Revert "drm/i915/gvt: Refine broken PPGTT scratch"

This reverts commit b20d09886fd1b74cd2255d846029a049e524db14.

This caused windows driver boot errors for invalid page address.
Revert for now.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Emulate PCI expansion ROM base address register
Changbin Du [Thu, 2 Nov 2017 05:33:42 +0000 (13:33 +0800)]
drm/i915/gvt: Emulate PCI expansion ROM base address register

Our vGPU doesn't have a device ROM, we need follow the PCI spec to
report this info to drivers. Otherwise, we would see below errors.

Inspecting possible rom at 0xfe049000 (vd=8086:1912 bdf=00:10.0)
qemu-system-x86_64: vfio-pci: Cannot read device rom at 00000000-0000-0000-0000-000000000001
Device option ROM contents are probably invalid (check dmesg).
Skip option ROM probe with rombar=0, or load from file with romfile=No option rom signature (got 4860)

I will also send a improvement patch to PCI subsystem related to PCI ROM.
But no idea to omit below error, since no pattern to detect vbios shadow
without touch its content.
0000:00:10.0: Invalid PCI ROM header signature: expecting 0xaa55, got 0x0000

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Make gvt_vgpu_err use pr_err
Changbin Du [Thu, 2 Nov 2017 05:33:32 +0000 (13:33 +0800)]
drm/i915/gvt: Make gvt_vgpu_err use pr_err

gvt_vgpu_err means something goes wrong. We need the error propagates to
kernel message by default.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Don't dump partial state in cmd parser
Changbin Du [Thu, 2 Nov 2017 05:33:23 +0000 (13:33 +0800)]
drm/i915/gvt: Don't dump partial state in cmd parser

I have seen the cmd parser dump partial odd info. Stop that and only dump
the full verbose info when debug enabled.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Reduce rcs mocs switch latency
Changbin Du [Mon, 30 Oct 2017 06:19:15 +0000 (14:19 +0800)]
drm/i915/gvt: Reduce rcs mocs switch latency

Use I915_WRITE_FW instead of I915_WRITE to reduce overhead.
The overall mmio switch latency lowers from ~600us to ~180us.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agoMAINTAINERS: Update gvt-linux.git new repo place
Zhenyu Wang [Thu, 26 Oct 2017 07:29:13 +0000 (15:29 +0800)]
MAINTAINERS: Update gvt-linux.git new repo place

gvt-linux.git repo is moved for its new place under
https://github.com/intel/gvt-linux.git

Old https://github.com/01org/gvt-linux.git is set
only for redirect now.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add new debugfs tool mmio_diff
Changbin Du [Mon, 23 Oct 2017 03:46:44 +0000 (11:46 +0800)]
drm/i915/gvt: Add new debugfs tool mmio_diff

This new debugfs entry is used to figure out which registers of vGPU
is different to host. It is a useful tool for new platform enabling
and debugging. When read this entry, all the diff mmio are recognized
and sorted by mmio offset. Besides, the bit positions of different
value are listed in 'Diff' column. Here is a show:

$ sudo cat ./mmio_diff
Offset   HW       vGPU     Diff
00002030 000025f8 00000000 3-8,10,13
00002034 012025f8 00000000 3-8,10,13,21,24
00002038 027fb000 00000000 12-13,15-22,25
0000203c 00003000 00000000 12-13
00002054 0000000a 00000040 1,3,6
00002074 012025f8 00000000 3-8,10,13,21,24
00002080 fffe6000 00000000 13-14,17-31
000020a8 fffffeff ffffffff 8
000020d4 00000004 00000000 2
....
00145974 eb42718c 010c11b0 2-5,13-14,17-19,22,25,27,29-31
00145978 0000002f 0000002a 0,2
0014597c 0000002f 0000002a 0,2
00145980 0000002b 00000028 0-1
00145984 a5a87c9e b27d20c0 1-4,6,10-12,14,16,18,20,22-26,28
001459c0 88390000 883c0000 16,18
00146200 88350000 883a0000 16-19
Total: 72432, Diff: 901

v3: fix a typo.
v2: add mmio_hw_access_pre/post().

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add mmio iterator intel_gvt_for_each_tracked_mmio()
Changbin Du [Mon, 23 Oct 2017 03:46:43 +0000 (11:46 +0800)]
drm/i915/gvt: Add mmio iterator intel_gvt_for_each_tracked_mmio()

This patch add a function intel_gvt_for_each_tracked_mmio() to
iterate each tracked mmio. The caller don't be aware of how the
tracked mmios are presented internally.

v2: remove snapshot_hw_mmio_registers().

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: opregion virtualization for win guest
Xiaolin Zhang [Fri, 20 Oct 2017 13:52:29 +0000 (21:52 +0800)]
drm/i915/gvt: opregion virtualization for win guest

this is an enhanced opregion emulation for win guest support
by initializing more data members including opregion header
size, version and child device propertity for display port.
for simplicity, redefined child_device_config structure.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: update CSB and CSB write pointer in virtual HWSP
Weinan Li [Fri, 20 Oct 2017 07:16:46 +0000 (15:16 +0800)]
drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

The engine provides a mirror of the CSB and CSB write pointer in the HWSP.
Read these status from virtual HWSP in VM can reduce CPU utilization while
applications have much more short GPU workloads. Here we update the
corresponding data in virtual HWSP as it in virtual MMIO.

Before read these status from HWSP in GVT-g VM, please ensure the host
support it by checking the BIT(3) of caps in PVINFO.

Virtual HWSP only support GEN8+ platform, since the HWSP MMIO may change
follow the platform update, please add the corresponding MMIO emulation
when enable new platforms in GVT-g.

v3 : Add address audit in HWSP address update.

v4 :
     Separate this patch with enalbe virtual HWSP in VM.
     Use intel_gvt_render_mmio_to_ring_id() to determine ring_id by offset.

v5 : Remove unnessary check about Gen8, GVT-g only support Gen8+.

Signed-off-by: Weinan Li <weinan.z.li@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Refine broken PPGTT scratch
Zhi Wang [Mon, 16 Oct 2017 18:00:27 +0000 (02:00 +0800)]
drm/i915/gvt: Refine broken PPGTT scratch

Refine previously broken PPGTT scratch. Scratch PTE was no correctly
handled and also the handling of scratch entries in page table walk was
not well organized, which brings gaps of introducing lazy shadow.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Introduce ops->set_present()
Zhi Wang [Tue, 10 Oct 2017 09:24:26 +0000 (17:24 +0800)]
drm/i915/gvt: Introduce ops->set_present()

We need ops->set_present() during generating a new scratch page table
entry.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Introduce page table type of current level in GTT type enumerations
Zhi Wang [Tue, 10 Oct 2017 09:19:30 +0000 (17:19 +0800)]
drm/i915/gvt: Introduce page table type of current level in GTT type enumerations

Need to figure out page table type of current level by GTT entry type
during getting a scratch page table entry.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Fix a bug of unexpectedly clear scratch page table
Zhi Wang [Tue, 10 Oct 2017 09:14:13 +0000 (17:14 +0800)]
drm/i915/gvt: Fix a bug of unexpectedly clear scratch page table

During a vGPU reset, the scratch page table shouldn't be cleared, what
needs to be cleared should be the scratch page.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Let the caller choose if a shadow page should be put into hash table
Zhi Wang [Tue, 10 Oct 2017 06:34:11 +0000 (14:34 +0800)]
drm/i915/gvt: Let the caller choose if a shadow page should be put into hash table

As we want to re-use intel_vgpu_shadow_page in buidling scrach page table
and we don't want to put scrach page table page into hash table, a new
param is introduced to give the caller a choice to decide if a shadow page
should be put into hash table.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Use I915_GTT_PAGE_SIZE
Zhi Wang [Tue, 10 Oct 2017 05:51:32 +0000 (13:51 +0800)]
drm/i915/gvt: Use I915_GTT_PAGE_SIZE

As there is already an I915_GTT_PAGE_SIZE marco in i915, let GVT-g use it
as well. Also this patch re-names some GTT marcos with additional prefix.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
Zhi Wang [Sat, 30 Sep 2017 09:42:20 +0000 (17:42 +0800)]
drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()

Since many emulation logic needs to convert the offset of ring registers
into ring id, we export it for other caller which might need it.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Factor intel_vgpu_page_track
Zhi Wang [Thu, 28 Sep 2017 18:47:55 +0000 (02:47 +0800)]
drm/i915/gvt: Factor intel_vgpu_page_track

As the data structure of "intel_vgpu_guest_page" will become much heavier
in future, it's better to factor out the guest memory page track mechnisim
as early as possible.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Refine shadow batch buffer
Zhi Wang [Sun, 24 Sep 2017 13:53:03 +0000 (21:53 +0800)]
drm/i915/gvt: Refine shadow batch buffer

1) Use standard i915 GEM object sequence to access the shadow batch buffer.
2) Manage i915 vma life cycle to solve one FIXME.

v2:
- Refine code structure.
- Refine the usage of GEM APIs.
- Add the missing lock/unlock in release_shadow_batch_buffer.

Test on my SKL NuC.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Refine find_bb_size()
Zhi Wang [Fri, 22 Sep 2017 13:12:03 +0000 (21:12 +0800)]
drm/i915/gvt: Refine find_bb_size()

Returns the error code if something is wrong and the size of batch buffer
is passed through the pointer.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Use BIT() to make klockwork happy
Zhi Wang [Tue, 26 Sep 2017 07:02:21 +0000 (15:02 +0800)]
drm/i915/gvt: Use BIT() to make klockwork happy

Replace the plain bit usage with BIT() to make klockwork happy.

Cc: Deng Hongyi <hongyi.deng@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Add basic debugfs infrastructure
Changbin Du [Tue, 26 Sep 2017 08:19:13 +0000 (16:19 +0800)]
drm/i915/gvt: Add basic debugfs infrastructure

We need debugfs entry to expose some debug information of gvt and vGPUs.
The first tool will be added is mmio-diff, which help to find the
difference values of host and vGPU mmio. It's useful for platform
enabling.

This patch just add a basic debugfs infrastructure, each vGPU has its own
sub-folder. Two simple attributes are created as a template.
.
├── num_tracked_mmio
├── vgpu1
|   └── active
└── vgpu2
    └── active

Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Refactor vGPU type code in kvmgt part
fred gao [Thu, 28 Sep 2017 03:03:03 +0000 (11:03 +0800)]
drm/i915/gvt: Refactor vGPU type code in kvmgt part

all the vGPU type related code in kvmgt will be moved into
gvt.c/gvt.h files while the common vGPU type related interfaces
will be called.

v2:
- intel_gvt_{init,cleanup}_vgpu_type_groups are initialized in
  gvt part. (Wang, Zhi)

Signed-off-by: fred gao <fred.gao@intel.com>
Reviewed-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Move vGPU type related code into gvt file
fred gao [Thu, 28 Sep 2017 03:03:02 +0000 (11:03 +0800)]
drm/i915/gvt: Move vGPU type related code into gvt file

In this patch, all the vGPU type related code will be merged into
same gvt file and the common interface will be exposed to both
XenGT and KvmGT.

v2:
- remove the useless mdev_* gvt_ops.
  add get_gvt_attr ops for MPT module.
  intel_gvt_{init,cleanup}_vgpu_type_groups are initialized in
  gvt part. (Wang, Zhi)
- set gvt_vgpu_type_groups[i] to NULL. (Zhang,Xiong)

Signed-off-by: fred gao <fred.gao@intel.com>
Reviewed-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Move clean_workloads() into scheduler.c
Zhi Wang [Tue, 12 Sep 2017 17:58:35 +0000 (01:58 +0800)]
drm/i915/gvt: Move clean_workloads() into scheduler.c

Move clean_workloads() into scheduler.c since it's not specific to
execlist.

v2:

- Remove clean_workloads in intel_vgpu_select_submission_ops. (Zhenyu)

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Introduce intel_vgpu_reset_submission
Zhi Wang [Tue, 12 Sep 2017 17:41:35 +0000 (01:41 +0800)]
drm/i915/gvt: Introduce intel_vgpu_reset_submission

Introduce an generic API to reset vGPU virtual submission interface.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Introduce vGPU submission ops
Zhi Wang [Tue, 12 Sep 2017 16:31:29 +0000 (00:31 +0800)]
drm/i915/gvt: Introduce vGPU submission ops

Introduce vGPU submission ops to support easy switching submission mode
of one vGPU between different OSes.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Remove one extra declaration in scheduler.h
Zhi Wang [Tue, 12 Sep 2017 14:39:08 +0000 (22:39 +0800)]
drm/i915/gvt: Remove one extra declaration in scheduler.h

Now the function has been moved into scheduler.c. The extra declaration
is not necessary.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Move common vGPU workload creation into scheduler.c
Zhi Wang [Tue, 12 Sep 2017 14:33:12 +0000 (22:33 +0800)]
drm/i915/gvt: Move common vGPU workload creation into scheduler.c

Move common vGPU workload creation functions into scheduler.c since
they are not specific to execlist emulation.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Move common workload preparation into prepare_workload()
Zhi Wang [Tue, 12 Sep 2017 14:06:39 +0000 (22:06 +0800)]
drm/i915/gvt: Move common workload preparation into prepare_workload()

Move common workload preparation into prepare_workload() in scheduler.c,
as they are not specific to execlist emulation.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Factor out prepare_workload()
Zhi Wang [Tue, 12 Sep 2017 13:51:10 +0000 (21:51 +0800)]
drm/i915/gvt: Factor out prepare_workload()

Factor out prepare_workload() for the following re-factor.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Factor out vGPU workload creation/destroy
Zhi Wang [Tue, 12 Sep 2017 13:42:09 +0000 (21:42 +0800)]
drm/i915/gvt: Factor out vGPU workload creation/destroy

Factor out vGPU workload creation/destroy functions since they are not
specific to execlist emulation.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Use dyndbg for gvt debug info
Shuo Liu [Thu, 21 Sep 2017 00:02:31 +0000 (08:02 +0800)]
drm/i915/gvt: Use dyndbg for gvt debug info

It's better enable/disable and classify gvt debug info dynamically.
This patch change it to dyndbg so can be dynamically enable/disable
each item. All gvt log can be enabled by,
 $ echo 'file *gvt* +p' > /sys/kernel/debug/dynamic_debug/control

Signed-off-by: Shuo Liu <shuo.a.liu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: ensure -ve return value is handled correctly
Colin Ian King [Tue, 19 Sep 2017 15:55:34 +0000 (16:55 +0100)]
drm/i915/gvt: ensure -ve return value is handled correctly

An earlier fix changed the return type from find_bb_size however the
integer return is being assigned to a unsigned int so the -ve error
check will never be detected. Make bb_size an int to fix this.

Detected by CoverityScan CID#1456886 ("Unsigned compared against 0")

Fixes: 1e3197d6ad73 ("drm/i915/gvt: Refine error handling for perform_bb_shadow")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add VM healthy check for submit_context
fred gao [Tue, 19 Sep 2017 07:11:29 +0000 (15:11 +0800)]
drm/i915/gvt: Add VM healthy check for submit_context

When a scan error occurs in submit_context, this patch is to
decrease the mm ref count and free the workload struct before
the workload is abandoned.

v2:
- submit_context related code should be combined together. (Zhenyu)

v3:
- free all the unsubmitted workloads. (Zhenyu)

v4:
- refine the clean path. (Zhenyu)

v5:
- polish the title. (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Add VM healthy check for workload_thread
fred gao [Tue, 19 Sep 2017 07:11:28 +0000 (15:11 +0800)]
drm/i915/gvt: Add VM healthy check for workload_thread

When a scan error occurs in dispatch_workload, this patch is to
check the healthy state and free all the queued workloads before
the failsafe mode is entered.

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Change the return type during command scan
fred gao [Tue, 19 Sep 2017 21:36:47 +0000 (05:36 +0800)]
drm/i915/gvt: Change the return type during command scan

Generally, there are 3 types of errors during command scan: a) some
commands might be unknown with EBADRQC;  b) some cmd access invalid
address with EFAULT; c) some unexpected force nonpriv cmd with EPERM.
later the healthy state can be judged through the return error.

v2:
- remove some internal i915 errors rating.  (Zhenyu)

v3:
- the healthy state is judged through the internal defined return
  error. (Zhenyu)
- force non priv cmd error can be ignored. (Kevin)

v4:
- reuse standard defined errno instead of recreate, e.g EBADRQC for
  unknown cmd, EFAULT for invalid address, EPERM for nonpriv. (Zhenyu)

v5:
- remove some irrelevant code for the patch.
- fix typo of vgpu_is_vm_unhealthy. (Zhenyu)

v6:
- move the healthy check and failsafe code into another patch. (Zhenyu)

v7:
- polish title and commit message. (Zhenyu)

Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915/gvt: Do not allocate initial ring scan buffer
Zhi Wang [Sun, 10 Sep 2017 14:01:10 +0000 (22:01 +0800)]
drm/i915/gvt: Do not allocate initial ring scan buffer

Theoretically, the largest bulk of commands in the ring buffer of an
engine might be the first submission, which usually contains a lot
of commands to initialize the HW. After removing the initial allocation
of the ring scan buffer and let krealloc() do everything we need, we
still have a big chance to get the buffer of suitable size in the first
submission.

Tested on my SKL NUC.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Move ring scan buffers into intel_vgpu_submission
Zhi Wang [Sun, 10 Sep 2017 13:58:11 +0000 (21:58 +0800)]
drm/i915/gvt: Move ring scan buffers into intel_vgpu_submission

Move ring scan buffers into intel_vgpu_submission since they belongs to
a part of vGPU submission stuffs.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Rename reserved ring buffer
Zhi Wang [Sun, 10 Sep 2017 13:46:06 +0000 (21:46 +0800)]
drm/i915/gvt: Rename reserved ring buffer

"reserved" means reserve something from somewhere. Actually they are
buffers used by command scanner. Rename it to ring_scan_buffer.

v2:

- Remove the usage of an extra variable. (Zhenyu)

Fixes: 0a53bc07f044 ("drm/i915/gvt: Separate cmd scan from request allocation")
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Fix a memory leak in cmd_parser.c
Zhi Wang [Sun, 10 Sep 2017 13:36:21 +0000 (21:36 +0800)]
drm/i915/gvt: Fix a memory leak in cmd_parser.c

The pointer points to the original memory can never take the return value
of krealloc().

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Move tlb_handle_pending into intel_vgpu_submission
Zhi Wang [Sun, 10 Sep 2017 13:33:20 +0000 (21:33 +0800)]
drm/i915/gvt: Move tlb_handle_pending into intel_vgpu_submission

Move tlb_handle_pending into intel_vgpu_submssion since it belongs to a
part of vGPU submission stuffs

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Introduce intel_vgpu_submission
Zhi Wang [Sun, 10 Sep 2017 13:15:18 +0000 (21:15 +0800)]
drm/i915/gvt: Introduce intel_vgpu_submission

Introduce intel_vgpu_submission to hold all members related to submission
in struct intel_vgpu before.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Move workload cache init/clean into intel_vgpu_{setup, clean}_submission()
Zhi Wang [Sun, 10 Sep 2017 12:28:09 +0000 (20:28 +0800)]
drm/i915/gvt: Move workload cache init/clean into intel_vgpu_{setup, clean}_submission()

Move vGPU workload cache initialization/de-initialization into
intel_vgpu_{setup, clean}_submission() since they are not specific to
execlist stuffs.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Rename intel_vgpu_{init, clean}_gvt_context()
Zhi Wang [Sun, 10 Sep 2017 12:08:18 +0000 (20:08 +0800)]
drm/i915/gvt: Rename intel_vgpu_{init, clean}_gvt_context()

To move workload related functions into scheduler.c, an expected way is
to collect all the init/clean functions related to vGPU workload
submission into fewer functions.

Rename intel_vgpu_{init, clean}_gvt_context() for above usage in future.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Make elsp_dwords in the right order
Zhi Wang [Sun, 10 Sep 2017 08:40:04 +0000 (16:40 +0800)]
drm/i915/gvt: Make elsp_dwords in the right order

The context descriptors in elsp_dwords are stored in a reversed order and
the definition of context descriptor is also reversed. The revesred stuff
is hard to be used and might cause misunderstanding. Make them in the right
oder for following code re-factoring.

Tested on my SKL NUC.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
7 years agodrm/i915/gvt: Add support for opregion virtualization
Xiaolin Zhang [Fri, 8 Sep 2017 13:37:48 +0000 (21:37 +0800)]
drm/i915/gvt: Add support for opregion virtualization

opregion emulated with a copy from host which leads to some display
bugs such as guest resolution adjustment failure due to host opregion
fail to claim port D support. with a fake opregion table provided
to fully emulate opregion to meet guest port requirement.

v1 - initial patch
v2 - reforamt opregion arrary with 0x02x output
v3 - opregion array removed with opregion generation on host initizaiton
v4 - rebased v3 patch from stable branch to staging branch which also has
     different struct child_device_config and addressed v3 review comments.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
7 years agodrm/i915: Remove pre-production pooled-EU w/a for Broxton
Chris Wilson [Tue, 14 Nov 2017 13:51:16 +0000 (13:51 +0000)]
drm/i915: Remove pre-production pooled-EU w/a for Broxton

WaEnablePooledEuFor2x6 only applies to preproduction models, unsupported
since commit 0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of
preproduction machines").

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114135116.30036-1-chris@chris-wilson.co.uk
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
7 years agodrm/i915: Make request's wait-for-space explicit
Chris Wilson [Wed, 15 Nov 2017 15:12:04 +0000 (15:12 +0000)]
drm/i915: Make request's wait-for-space explicit

At the start of building a request, we would wait for roughly enough
space to fit the average request (to reduce the likelihood of having to
wait and abort partway through request construction). To achieve we
would try to begin a 0-length command packet, this just adds extra
confusion so make the wait-for-space explicit, as in the next patch we
want to move it from the backend to the i915_gem_request_alloc() so it
can ensure that the wait-for-space is the first operation in building a
new request.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171115151204.8105-2-chris@chris-wilson.co.uk
7 years agodrm/i915/selftests: Increase size for mock ringbuffer
Chris Wilson [Wed, 15 Nov 2017 15:12:03 +0000 (15:12 +0000)]
drm/i915/selftests: Increase size for mock ringbuffer

We don't actually emit any commands into the ringbuffer, so we set it
very small. However, an upcoming change centralises the wait-for-space
into i915_gem_request_alloc() and that imposes a minimum size upon all
ringbuffers (mock or real) of MIN_SPACE_FOR_ADD_REQUEST. Grow the
mock ringbuffer such that we allocate a single page for the struct+buffer,
satisfying the new condition without wasting too much space.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171115151204.8105-1-chris@chris-wilson.co.uk
7 years agodrm/i915: Initialise entry in intel_ppat_get() for older compilers
Chris Wilson [Wed, 15 Nov 2017 13:17:05 +0000 (13:17 +0000)]
drm/i915: Initialise entry in intel_ppat_get() for older compilers

gcc-4.7.3 is confused by the guards inside intel_ppat_get() and reports:

drivers/gpu/drm/i915/i915_gem_gtt.c: In function ‘intel_ppat_get’:
drivers/gpu/drm/i915/i915_gem_gtt.c:3044:27: warning: ‘entry’ may be used uninitialized in this function [-Wmaybe-uninitialized]

Forgive the compiler this once, and rearrange the code so that entry is
always initialised.

v2: Flavour with a bit of NULL (instead of ERR_PTR(-ENOSPC))

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171115131705.16341-1-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agodrm/i915/selftests: Markup __iomem for igt_gem_coherency
Chris Wilson [Tue, 14 Nov 2017 19:18:42 +0000 (19:18 +0000)]
drm/i915/selftests: Markup __iomem for igt_gem_coherency

Silence sparse warnings by using __iomem markup and io accessors.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114191842.19063-1-chris@chris-wilson.co.uk
7 years agodrm/i915: Use ELK stolen memory reserved detection for ILK
Ville Syrjälä [Thu, 2 Nov 2017 15:17:37 +0000 (17:17 +0200)]
drm/i915: Use ELK stolen memory reserved detection for ILK

While I have no solid proof that ILK follows the ELK path when it
comes to the stolen memory reserved area, there are some hints that
it might be the case. Unfortunately my ILK doesn't have this enabled,
and no way to enable it via the BIOS it seems.

So let's have ILK use the ELK code path, and let's toss in a WARN
into the code to see if we catch anyone with an ILK that has this
enabled to further analyze the situation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171102151737.23336-3-ville.syrjala@linux.intel.com
Acked-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
7 years agodrm/i915: Make the report about a bogus stolen reserved area an error
Ville Syrjälä [Thu, 2 Nov 2017 15:17:36 +0000 (17:17 +0200)]
drm/i915: Make the report about a bogus stolen reserved area an error

Now that we should be properly filtering out the cases when the stolen
reserved area is disabled, let's convert the debug message about a
misplaced reserved area into an error.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171102151737.23336-2-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
7 years agodrm/i915: Check if the stolen memory "reserved" area is enabled or not
Ville Syrjälä [Thu, 2 Nov 2017 15:17:35 +0000 (17:17 +0200)]
drm/i915: Check if the stolen memory "reserved" area is enabled or not

Apparently there are some machines that put semi-sensible looking values
into the stolen "reserved" base and size, except those values are actually
outside the stolen memory. There is a bit in the register which
supposedly could tell us whether the reserved area is even enabled or
not. Let's check for that before we go trusting the base and size.

Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171102151737.23336-1-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
7 years agodrm/i915: Fix kerneldocs for intel_audio.c
Ville Syrjälä [Tue, 14 Nov 2017 19:11:27 +0000 (21:11 +0200)]
drm/i915: Fix kerneldocs for intel_audio.c

Fix copy/paste fail in kerneldocs for intel_audio_codec_disable().

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114191127.16188-1-ville.syrjala@linux.intel.com
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
7 years agodrm/i915: Call uncore_suspend before platform suspend handlers
Hans de Goede [Tue, 14 Nov 2017 13:55:18 +0000 (14:55 +0100)]
drm/i915: Call uncore_suspend before platform suspend handlers

Quoting Ville: "the forcewake timer might still be active until the uncore
suspend, and having active forcewakes while we've already told the GT wake
stuff to stop acting normally doesn't seem quite right to me."

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114135518.15981-3-hdegoede@redhat.com
7 years agodrm/i915: Re-register PMIC bus access notifier on runtime resume
Hans de Goede [Tue, 14 Nov 2017 13:55:17 +0000 (14:55 +0100)]
drm/i915: Re-register PMIC bus access notifier on runtime resume

intel_uncore_suspend() unregisters the uncore code's PMIC bus access
notifier and gets called on both normal and runtime suspend.

intel_uncore_resume_early() re-registers the notifier, but only on
normal resume. Add a new intel_uncore_runtime_resume() function which
only re-registers the notifier and call that on runtime resume.

Cc: stable@vger.kernel.org
Reported-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114135518.15981-2-hdegoede@redhat.com
7 years agodrm/i915: Fix false-positive assert_rpm_wakelock_held in i915_pmic_bus_access_notifier v2
Hans de Goede [Fri, 10 Nov 2017 15:03:01 +0000 (16:03 +0100)]
drm/i915: Fix false-positive assert_rpm_wakelock_held in i915_pmic_bus_access_notifier v2

assert_rpm_wakelock_held is triggered from i915_pmic_bus_access_notifier
even though it gets unregistered on (runtime) suspend, this is caused
by a race happening under the following circumstances:

intel_runtime_pm_put does:

   atomic_dec(&dev_priv->pm.wakeref_count);

   pm_runtime_mark_last_busy(kdev);
   pm_runtime_put_autosuspend(kdev);

And pm_runtime_put_autosuspend calls intel_runtime_suspend from
a workqueue, so there is ample of time between the atomic_dec() and
intel_runtime_suspend() unregistering the notifier. If the notifier
gets called in this windowd assert_rpm_wakelock_held falsely triggers
(at this point we're not runtime-suspended yet).

This commit adds disable_rpm_wakeref_asserts and
enable_rpm_wakeref_asserts calls around the
intel_uncore_forcewake_get(FORCEWAKE_ALL) call in
i915_pmic_bus_access_notifier fixing the false-positive WARN_ON.

Changes in v2:
-Reword comment explaining why disabling the wakeref asserts is
 ok and necessary

Cc: stable@vger.kernel.org
Reported-by: FKr <bugs-freedesktop@ubermail.me>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171110150301.9601-2-hdegoede@redhat.com
7 years agodrm/i915/selftests: Always initialise err
Chris Wilson [Tue, 14 Nov 2017 22:33:46 +0000 (22:33 +0000)]
drm/i915/selftests: Always initialise err

smatch does not track initialised values as well as gcc, and this
triggers many warnings by smatch not presented by gcc. Silence smatch by
initialising the error values to -ENODEV, which we use to denote
internal errors. (If we see a selftest fail with a silent -ENODEV, we
know smatch was right!)

v2: smatch was right about igt_create_vma(), it may unlikely fail on the
first object allocation which we want to be loud about.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114223346.25958-1-chris@chris-wilson.co.uk
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
7 years agodrm/i915: Resume GuC before using GEM
Chris Wilson [Tue, 14 Nov 2017 13:03:00 +0000 (13:03 +0000)]
drm/i915: Resume GuC before using GEM

Resuming GEM presumes it can talk to hw, in particular to ensure the
kernel context is loaded upon resume for powersaving. If the GuC is
still asleep at this point, we upset the HW. Rearrange the resume such
that we restore the original order of init-hw, resume-guc, use-gem.

Fixes: 37cd33006d02 ("drm/i915: Remove redundant intel_autoenable_gt_powersave()")
References: a1c419941453 ("drm/i915/guc: Add host2guc notification for suspend and resume")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Alex Dai <yu.dai@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114130300.25677-2-chris@chris-wilson.co.uk
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
7 years agodrm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glk
Rodrigo Vivi [Sat, 11 Nov 2017 00:03:19 +0000 (16:03 -0800)]
drm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glk

Display is not sending a PMRsp when a PMReq is received
at the same time that all planes are turned off.
State machine in the dcprunit is stuck in the WAIT4DONE
state which means that there is no fill_done.

WA: disable arbiter clock gating, set bit [27] of 0x46530

v2: As Ville pointed out, based on the description the issue
    can happen when disabling the planes, similar to
    WaRsPkgCStateDisplayPMReq:hsw
    Also description of the issue was updated on commit
    message to make it more clear that we need this
    earlier.
v3: Restore comment about possibility to system hang
    to where we are sure about it, without speculation. (Ville).
v4: Remove doubled sob. Actually do v3 changes :/

Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171111000319.5040-1-rodrigo.vivi@intel.com
7 years agoMerge airlied/drm-next into drm-intel-next-queued
Rodrigo Vivi [Tue, 14 Nov 2017 15:43:00 +0000 (07:43 -0800)]
Merge airlied/drm-next into drm-intel-next-queued

Catchup with upstream.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
7 years agodrm/i915: Unconditionally apply the Broxton register workaround set
Chris Wilson [Tue, 14 Nov 2017 13:43:40 +0000 (13:43 +0000)]
drm/i915: Unconditionally apply the Broxton register workaround set

Having removed the preproduction Broxton support (see commit 0102ba1fd8af
("drm/i915: Add early BXT sdv to the list of preproduction machines")),
we know we then always need the production Broxton workaround set and do
not need a predicate upon revision.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114134340.5439-2-chris@chris-wilson.co.uk
7 years agodrm/i915: Remove pre-production Broxton register workarounds
Chris Wilson [Tue, 14 Nov 2017 13:43:39 +0000 (13:43 +0000)]
drm/i915: Remove pre-production Broxton register workarounds

We've begun excluding pre-production Broxton machines since commit
0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of preproduction
machines"), now remove the list of workaround register values for those
early machines.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170927093325.24206-1-chris@chris-wilson.co.uk
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114134340.5439-1-chris@chris-wilson.co.uk
7 years agodrm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnl
Chris Wilson [Sat, 11 Nov 2017 10:03:36 +0000 (10:03 +0000)]
drm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnl

gem_workarounds reports that the SLICE_UNIT_LEVEL_CLKGATE write isn't
sticking. Commit 0a60797a0efb ("drm/i915: Implement
ReadHitWriteOnlyDisable.") presumes that SLICE_UNIT_LEVEL_CLKGATE is a
masked register in the context image, but commit 90007bca6162
("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") lists it as
an ordering unmasked register. The masked write will be losing the
default settings if we trust the original commit. That gem_workarounds
reports the value is lost entirely is more worrying though -- but it
clearly suggests that it is not a masked register in the context image,
so unify both w/a to use the original rmw.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103705
Fixes: 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.")
References: 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171111100336.11020-1-chris@chris-wilson.co.uk
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
7 years agodrm/i915: fix 64bit divide
Lionel Landwerlin [Mon, 13 Nov 2017 23:34:53 +0000 (23:34 +0000)]
drm/i915: fix 64bit divide

ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!

Store the frequency in kHz and drop 64bit divisions.

v2: Use div64_u64 (Matthew)

v3: store frequency in kHz to avoid 64bit divs (Chris/Ville)

Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to userspace")
Reported-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-3-lionel.g.landwerlin@intel.com
Reviewed-by: Ewelina Musial <ewelina.musial@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agodrm/i915: Generalize transcoder looping
Mika Kahola [Thu, 9 Nov 2017 08:37:50 +0000 (10:37 +0200)]
drm/i915: Generalize transcoder looping

To make looping through transcoders in intel_ddi.c more generic, let's switch
to use 'for_each_pipe()' macro to do this.

v2: Add a notion that we are dealing with transcoders instead of pipes (Jani)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1510216670-16848-1-git-send-email-mika.kahola@intel.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agodrm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+
James Ausmus [Mon, 13 Nov 2017 18:11:28 +0000 (10:11 -0800)]
drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

v4: Consolidate skl_plane_ctl_format switch statement on formats that
return the same settings. (Ville)

Signed-off-by: James Ausmus <james.ausmus@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113181128.2926-1-james.ausmus@intel.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
7 years agodrm/i915: Introduce GEM proxy
Tina Zhang [Tue, 14 Nov 2017 10:25:13 +0000 (10:25 +0000)]
drm/i915: Introduce GEM proxy

GEM proxy is a kind of GEM, whose backing physical memory is pinned
and produced by guest VM and is used by host as read only. With GEM
proxy, host is able to access guest physical memory through GEM object
interface. As GEM proxy is such a special kind of GEM, a new flag
I915_GEM_OBJECT_IS_PROXY is introduced to ban host from changing the
backing storage of GEM proxy.

v3:
- update "Reviewed-by". (Joonas)

v2:
- return -ENXIO when pin and map pages of GEM proxy to kernel space.
  (Chris)

Here are the histories of this patch in "Dma-buf support for Gvt-g"
patch-set:

v14:
- return -ENXIO when gem proxy object is banned by ioctl.
  (Chris) (Daniel)

v13:
- add comments to GEM proxy. (Chris)
- don't ban GEM proxy in i915_gem_sw_finish_ioctl. (Chris)
- check GEM proxy bar after finishing i915_gem_object_wait. (Chris)
- remove GEM proxy bar in i915_gem_madvise_ioctl.

v6:
- add gem proxy barrier in the following ioctls. (Chris)
  i915_gem_set_caching_ioctl
  i915_gem_set_domain_ioctl
  i915_gem_sw_finish_ioctl
  i915_gem_set_tiling_ioctl
  i915_gem_madvise_ioctl

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v1
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/1510555798-21079-2-git-send-email-tina.zhang@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114102513.22269-2-chris@chris-wilson.co.uk
7 years agodrm/i915: Object w/o backing storage is banned by -ENXIO
Tina Zhang [Tue, 14 Nov 2017 10:25:12 +0000 (10:25 +0000)]
drm/i915: Object w/o backing storage is banned by -ENXIO

-ENXIO should be returned when operations are banned from changing
backing storage of objects without backing storage.

v4:
- update "Reviewed-by". (Joonas)

v3:
- separate this patch from "Introduce GEM proxy" patch-set. (Joonas)

v2:
- update the patch description and subject to just mention objects w/o
  backing storage, instead of "GEM proxy". (Joonas)

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1510555798-21079-1-git-send-email-tina.zhang@intel.com
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114102513.22269-1-chris@chris-wilson.co.uk
7 years agodrm/i915: Fix function name in comment
Lucas De Marchi [Tue, 14 Nov 2017 00:46:38 +0000 (16:46 -0800)]
drm/i915: Fix function name in comment

Commit 78597996370c (drm/i915/bxt: Fix PPS lost state after suspend
breaking eDP link training) renamed the function to
intel_power_sequencer_reset() but forgot to update comment.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114004638.5186-1-lucas.demarchi@intel.com
7 years agoMerge tag 'exynos-drm-next-for-v4.15' of git://git.kernel.org/pub/scm/linux/kernel...
Dave Airlie [Tue, 14 Nov 2017 04:12:43 +0000 (14:12 +1000)]
Merge tag 'exynos-drm-next-for-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next

- Improved HDMI and Mixer drivers
  . It moves mode setup and plane update code to commit
    like other CRTC drivers
  . It makes mode commit to be called in enable callback only one time
  . some cleanup and fixup to HDMI and Mixer drivers.
  . It adds 1024x768, 1280x1024 and 1366x768 modes support
- Added HDMI audio interface driver
  . As of now, HDMI audio worked on boards with external audio codec connected
    in parallel with the HDMI audio transmitter's I2S interface.
    This patch is required to support HDMI audio properly.

* tag 'exynos-drm-next-for-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos:
  drm: exynos: Add driver for HDMI audio interface
  drm/exynos/hdmi: add 85.5MHz pixel clock for v14 HDMI PHY
  drm/exynos/mixer: enable support for 1024x768 and 1280x1024 modes
  drm/exynos/hdmi: quirk for support mode timings conversion
  drm/exynos/mixer: pass actual mode on MIXER to encoder
  drm/exynos: add mode_fixup callback to exynos_drm_crtc_ops
  drm/exynos/hdmi: remove redundant mode field
  drm/exynos/mixer: remove mixer_resources sub-structure
  drm/exynos/mixer: fix mode validation code
  drm/exynos/mixer: move resolution configuration to single function
  drm/exynos/mixer: move mode commit to enable callback
  drm/exynos/mixer: abstract out output mode setup code

7 years agoMerge branch 'linus-4.14-rc4-acp-prereq' of git://people.freedesktop.org/~agd5f/linux...
Dave Airlie [Mon, 13 Nov 2017 19:53:39 +0000 (05:53 +1000)]
Merge branch 'linus-4.14-rc4-acp-prereq' of git://people.freedesktop.org/~agd5f/linux into drm-next

This is a shared tree between drm and audio for some amd bits.

* 'linus-4.14-rc4-acp-prereq' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu Moving amdgpu asic types to a separate file
  ASoC: AMD: Added asic_type as ACP DMA driver platform data
  drm/amd/amdgpu: Added asic_type as ACP DMA driver platform data

7 years agoMerge tag 'drm-misc-fixes-2017-11-13' of git://anongit.freedesktop.org/drm/drm-misc...
Dave Airlie [Mon, 13 Nov 2017 19:29:34 +0000 (05:29 +1000)]
Merge tag 'drm-misc-fixes-2017-11-13' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

Driver Changes:
- qxl: Use a shadow bo as primary and blit to it to fix flicker (Gerd)
- rockchip: Convert psr spinlock to mutex (Emil)

Cc: Emil Renner Berthing <kernel@esmil.dk>
Cc: Gerd Hoffmann <kraxel@redhat.com>
* tag 'drm-misc-fixes-2017-11-13' of git://anongit.freedesktop.org/drm/drm-misc:
  drm/rockchip: analogix_dp: Use mutex rather than spinlock

7 years agoMerge tag 'drm-intel-next-fixes-2017-11-10' of git://anongit.freedesktop.org/drm...
Dave Airlie [Mon, 13 Nov 2017 19:18:21 +0000 (05:18 +1000)]
Merge tag 'drm-intel-next-fixes-2017-11-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

drm/i915 fixes for v4.15

* tag 'drm-intel-next-fixes-2017-11-10' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915: Reorder context-close to avoid calling i915_vma_close() under RCU
  drm/i915: Move init_clock_gating() back to where it was
  drm/i915: Prune the reservation shared fence array
  drm/i915: Idle the GPU before shinking everything
  drm/i915: Lock llist_del_first() vs llist_del_all()
  drm/i915: Calculate ironlake intermediate watermarks correctly, v2.
  drm/i915: Disable lazy PPGTT page table optimization for vGPU
  drm/i915/execlists: Remove the priority "optimisation"
  drm/i915: Filter out spurious execlists context-switch interrupts