Okash Khawaja [Fri, 4 Nov 2022 12:38:01 +0000 (12:38 +0000)]
feat(cpus): make cache ops conditional
When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset. Similarly, debug recovery mode of DynamIQ
cluster ensures that contents of the shared L3 cache are also not
invalidated upon transition to On mode.
Booting cores in debug recovery mode means booting with caches disabled
and preserving the caches until a point where software can dump the
caches and retrieve their contents. TF-A however unconditionally cleans
and invalidates caches at multiple points during boot. This can lead to
memory corruption as well as loss of cache contents to be used for
debugging.
This patch fixes this by calling a platform hook before performing CMOs
in helper routines in cache_helpers.S. The platform hook plat_can_cmo is
an assembly routine which must not clobber x2 and x3, and avoid using
stack. The whole checking is conditional upon `CONDITIONAL_CMO` which
can be set at compile time.
This patch adds the following changes to complete the existing
TRNG implementation:
1. Adds a feature specific scope for buildlog generation.
2. Updates the docs on the build flag "TRNG_SUPPORT" and its values.
3. Makefile update and improves the existing comments at few sections
for better understanding of the underlying logic.
- Remove mentions of Arm SGM-775 and MediaTek MT6795 platforms.
Both platform ports were deleted from TF-A source tree in the
last release (v2.7).
- Remove mention of Arm Morello platform, as it now has a dedicated
documentation page accessible from the table of contents
(see docs/plat/arm/morello/).
Olivier Deprez [Tue, 11 Oct 2022 13:38:27 +0000 (15:38 +0200)]
feat: pass SMCCCv1.3 SVE hint bit to dispatchers
SMCCCv1.3 introduces the SVE hint bit added to the SMC FID (bit 16)
denoting that the world issuing an SMC doesn't expect the callee to
preserve the SVE state (FFR, predicates, Zn vector bits greater than
127). Update the generic SMC handler to copy the SVE hint bit state
to SMC flags and mask out the bit by default for the services called
by the standard dispatcher. It is permitted by the SMCCC standard to
ignore the bit as long as the SVE state is preserved. In any case a
callee must preserve the NEON state (FPCR/FPSR, Vn 128b vectors)
whichever the SVE hint bit state.
This change updates the version of the Node Version Manager suggested by
the prerequisites documentation. The NVM installation command line hint
has been replaced with the snippet provided by NVM's user guide, and the
second line now automatically installs a version of Node.js compatible
with TF-A's repository scripts.
Change-Id: I6ef5e504118238716ceb45a52083450c424c5d20 Signed-off-by: Chris Kay <chris.kay@arm.com>
Olivier Deprez [Fri, 4 Nov 2022 09:47:54 +0000 (10:47 +0100)]
Merge changes from topic "hikey960-el3-spmc" into integration
* changes:
feat(hikey960): read serial number from UFS
feat(hikey960): add a FF-A logical partition
feat(hikey960): add memory sharing hooks for SPMC_AT_EL3
feat(hikey960): add plat-defines for SPMC_AT_EL3
feat(hikey960): define a datastore for SPMC_AT_EL3
feat(hikey960): add SP manifest for SPMC_AT_EL3
feat(hikey960): increase secure workspace to 64MB
feat(hikey960): upgrade to xlat_tables_v2
feat(drtm): add DRTM parameters structure version check
Added DRTM parameters structure version check that as per
the current released DRTM specification [1].
Mainly to cater below mentioned in the specification [1]
section 3.12 -
For a given DRTM major version number this structure will
always be extended in a backwards compatible manner.
vallau01 [Mon, 8 Aug 2022 12:10:14 +0000 (14:10 +0200)]
fix(el3-spmc): compute full FF-A V1.1 desc size
This patch fixes an issue in spmc_ffa_fill_desc.
In order to compute the spmc_shm_get_v1_1_descriptor_size,
fragment_length which is a fraction of the descriptor size is used as
desc_size parameter. It has to be replaced with the
full V1.0 descriptor size(obj->desc_filled).
Boyan Karatotev [Mon, 3 Oct 2022 13:21:28 +0000 (14:21 +0100)]
fix(cpus): workaround for Cortex-A710 erratum 2291219
Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Boyan Karatotev [Mon, 3 Oct 2022 13:18:28 +0000 (14:18 +0100)]
fix(cpus): workaround for Cortex-X3 erratum 2313909
Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions
r0p0 and r1p0, and is fixed in r1p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest
Boyan Karatotev [Mon, 3 Oct 2022 13:07:08 +0000 (14:07 +0100)]
fix(cpus): workaround for Neoverse-N2 erratum 2326639
Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to
1 before the power down sequence that sets CORE_PWRDN_EN. This allows
the cpu to retry the power down and prevents the deadlock. TF-A never
clears this bit even if it wakes up from the wfi in the sequence since
it is not expected to do anything but retry to power down after and the
bit is cleared on reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest/
Platforms which implement pwr_domain_pwr_down_wfi differ substantially
in behaviour. However, different cpus require similar sequences to power
down. This patch tightens the behaviour of these platforms to end on a
wfi loop after performing platform power down. This is required so that
platforms behave more consistently on power down, in cases where the wfi
can fall through.
Add documentation how to build EL3 SPMC,
briefly describes all FF-A interfaces,
SP boot flow, SP Manifest, Power Management,
Boot Info Protocol, Runtime model and state
transition and Interrupt Handling.
Boyan Karatotev [Tue, 25 Oct 2022 10:29:04 +0000 (11:29 +0100)]
chore: rename Makalu ELP to Cortex-X3
The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.
Bipin Ravi [Thu, 13 Oct 2022 22:25:51 +0000 (17:25 -0500)]
fix(security): optimisations for CVE-2022-23960
Optimised the loop workaround for Spectre_BHB mitigation:
1. use of speculation barrier for cores implementing SB instruction.
2. use str/ldr instead of stp/ldp as the loop uses only X2 register.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I8ac53ea1e42407ad8004c1d59c05f791011f195d
Shawn Guo [Wed, 26 Oct 2022 08:38:53 +0000 (16:38 +0800)]
fix(imx8m): update poweroff related SNVS_LPCR bits only
Function imx_system_off() writes SNVS_LPCR register to power off the SoC
without bit masking. This clears other bits like LPWUI_EN and breaks
the function of SoC wake-up using RTC alarm. Fix it by updating poweroff
related bits only.
Fixed the qemu 32 bit clang build fail caused because of
no march32 directives in TF_CFLAGS_aarch32 variable
march32_directive is initialized later in Makefile and since clang build
uses Immediate set instead of Lazy set , TF_CFLAGS_aarch32 doesn't
have mcpu variable.
Daniel Boulby [Wed, 5 Oct 2022 10:05:22 +0000 (11:05 +0100)]
feat(zlib): update zlib source files
Upgrade the zlib source files to the ones present in the version 1.2.13
of zlib [1]. Since 1.2.11 the use of Arm crc32 instructions has been
introduced so update the files to make use of this.
[1] https://github.com/madler/zlib/tree/v1.2.13
Change-Id: Ideef78c56f05ae7daec390d00dcaa8f66b18729e Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Merge changes from topic "imx8m-hab-support" into integration
* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and map required memory blocks
feat(imx8mn): add hab and map required memory blocks
feat(imx8mm): add hab and map required memory blocks
build: deprecate Arm rdn1edge and sgi575 FVP platforms
Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discontinued. rdn1edge platform has been superseded by the
rdn2 platform, which is already supported in TF-A and CI work is
underway for this platform.
Change-Id: If2228fb73549b244c3a5b0e5746617b3f24fe771 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Marco Felsch [Mon, 22 Aug 2022 10:39:01 +0000 (12:39 +0200)]
feat(imx8mm): add BL31 PIE support
Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). For the PIE support we only need to replace the
BL31_BASE define by the BL31_START symbol which is a relocatable and we
need to enable it by setting ENABLE_PIE := 1.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I52e654917167f0faf6aa437da233d8faf1f2bb26
Marco Felsch [Mon, 22 Aug 2022 10:30:11 +0000 (12:30 +0200)]
refactor(imx8mm): introduce BL2_SIZE and BL31_SIZE
No functional change.
Introduce BLx_SIZE defines and calculate the limits based on the
BLx_BASE and the BLx_SIZE define. Also make use of SZ_128K to make it
easier to read. This is required for later BL31 PIE support since it
drops the calculation based on the BL31_LIMIT and BL31_BASE.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I8670faa5d5a572ef230011594f3d0d594fb257d9
Marco Felsch [Mon, 22 Aug 2022 10:25:04 +0000 (12:25 +0200)]
refactor(imx8mm): make use of setup_page_tables()
No functional change. Use the setup_page_tables() helper function which
does the three calls for us. Also the function has some logging support
which will be nice during debugging.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Ic465491ff5468e812e805de56be3b6b92d245080
Marco Felsch [Mon, 22 Aug 2022 10:23:56 +0000 (12:23 +0200)]
refactor(imx8mm): cleanup the mmap region settings
No functional change.
Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed to mmap_add() to map
all regions. While on it introduce some defines so the addr, size and
flags can be read more easily.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I9f0ae9fc89514db71bef734b867c46574833831c
Marco Felsch [Mon, 4 Jul 2022 10:18:34 +0000 (12:18 +0200)]
feat(imx8mn): add BL31 PIE support
Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). For the PIE support we only need to replace the
BL31_BASE define by the BL31_START symbol which is a relocatable and we
need to enable it by setting ENABLE_PIE := 1.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I33c8e35c35112d70d2725eebe484a853a8aad9e0
Marco Felsch [Mon, 4 Jul 2022 10:14:54 +0000 (12:14 +0200)]
refactor(imx8mn): introduce BL31_SIZE
Introduce BL31_SIZE define and calculate the limit based on the
BL31_BASE and the BL31_SIZE define. Also make use of SZ_128K to make it
easier to read. This is required for later BL31 PIE support since it
drops the calculation based on the BL31_LIMIT and BL31_BASE.
While on it remove the duplicated <lib/utils_def.h> include.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Ifca40bd5682ef993db986439115abd9e9a66a5b2
Marco Felsch [Mon, 4 Jul 2022 10:11:01 +0000 (12:11 +0200)]
refactor(imx8mn): make use of setup_page_tables()
No functional change.
Use the setup_page_tables() helper function which does the three calls
for us. Also the function has some logging support which will be nice
during debugging.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I2f0182f19300a3a57bbeb7e2107c5fb5525dd0c1
Marco Felsch [Mon, 4 Jul 2022 10:07:59 +0000 (12:07 +0200)]
refactor(imx8mn): cleanup the mmap region settings
No functional change.
Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed to mmap_add() to map
all regions. While on it introduce some defines so the addr, size and
flags can be read more easily.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Id5849d2a7326a943927f458f1c6abbc041f5be18
Marco Felsch [Fri, 1 Jul 2022 13:55:30 +0000 (15:55 +0200)]
feat(imx8mp): add BL31 PIE support
Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). How important this is shows the back and forth
of the BL31_BASE address starting with TF-A v2.5. Since then the
BL31_BASE address wasn't stable and choosing the correct combination of
SPL version loadaddress and TF-A version loadaddr was tricky.
For the PIE support we only need to replace the BL31_BASE by the
BL31_START which is a relocatable symbol and to enable it by setting
ENABLE_PIE := 1.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I4214db1f27120f9f9cd1413ccd7a5a7d095ff45d
projects / arm-tf.git / log