From: Guo Ren Date: Sun, 5 Jan 2020 02:52:14 +0000 (+0800) Subject: riscv: Fixup obvious bug for fp-regs reset X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=dc6fcba72f0435b7884f2e92fd634bb9f78a2c60;p=kernel.git riscv: Fixup obvious bug for fp-regs reset CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine ISA Register misa. Every bit:1 indicate a feature, so we should beqz reset_done when there is no F/D bit in csr_misa register. Signed-off-by: Guo Ren [paul.walmsley@sifive.com: fix typo in commit message] Fixes: 9e80635619b51 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Paul Walmsley --- diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 797802c73dee2..2227db63f8955 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -251,7 +251,7 @@ ENTRY(reset_regs) #ifdef CONFIG_FPU csrr t0, CSR_MISA andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) - bnez t0, .Lreset_regs_done + beqz t0, .Lreset_regs_done li t1, SR_FS csrs CSR_STATUS, t1